On Thu, Dec 23, 2021 at 02:05:40AM +0800, Rafael J. Wysocki wrote:

On Wed, Dec 22, 2021 at 1:17 AM Huang Rui [off-list ref] wrote:

quoted

Hi Boris,

On Tue, Dec 21, 2021 at 11:45:09PM +0800, Borislav Petkov wrote:

quoted

On Mon, Dec 20, 2021 at 12:35:16AM +0800, Huang Rui wrote:

Capitalize subject's first letter:
 [x86/msr: add AMD CPPC MSR definitions]
 [x86/msr: Add AMD CPPC MSR definitions]

Thank you for the reply! Updated.

quoted

quoted

AMD CPPC (Collaborative Processor Performance Control) function uses MSR
registers to manage the performance hints. So add the MSR register macro
here.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 arch/x86/include/asm/msr-index.h | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 01e2650b9585..e7945ef6a8df 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h

@@ -486,6 +486,23 @@

 #define MSR_AMD64_VIRT_SPEC_CTRL   0xc001011f

+/* AMD Collaborative Processor Performance Control MSRs */
+#define MSR_AMD_CPPC_CAP1          0xc00102b0
+#define MSR_AMD_CPPC_ENABLE                0xc00102b1
+#define MSR_AMD_CPPC_CAP2          0xc00102b2
+#define MSR_AMD_CPPC_REQ           0xc00102b3
+#define MSR_AMD_CPPC_STATUS                0xc00102b4
+
+#define CAP1_LOWEST_PERF(x)        (((x) >> 0) & 0xff)
+#define CAP1_LOWNONLIN_PERF(x)     (((x) >> 8) & 0xff)
+#define CAP1_NOMINAL_PERF(x)       (((x) >> 16) & 0xff)
+#define CAP1_HIGHEST_PERF(x)       (((x) >> 24) & 0xff)
+
+#define REQ_MAX_PERF(x)            (((x) & 0xff) << 0)
+#define REQ_MIN_PERF(x)            (((x) & 0xff) << 8)
+#define REQ_DES_PERF(x)            (((x) & 0xff) << 16)
+#define REQ_ENERGY_PERF_PREF(x)    (((x) & 0xff) << 24)

All those bitfield names are too generic - they should at least be
prefixed with "CPPC_"

If an Intel CPPC set of MSRs appears too, then the prefix should be
"AMD_CPPC_" and so on.

The similar function in Intel names HWP (Hardware P-State), and related MSR
registers names as "HWP_" as the prefixes like below:

/* IA32_HWP_CAPABILITIES */
#define HWP_HIGHEST_PERF(x)             (((x) >> 0) & 0xff)
#define HWP_GUARANTEED_PERF(x)          (((x) >> 8) & 0xff)
#define HWP_MOSTEFFICIENT_PERF(x)       (((x) >> 16) & 0xff)
#define HWP_LOWEST_PERF(x)              (((x) >> 24) & 0xff)

Hi Rafael,

Can we use the "CPPC_" as the prefixes for AMD CPPC MSR bitfield name?

Well, what about using "AMD_CPPC_" instead of "REQ_" in these names?
The names of the analogous Intel macros start with "HWP_" which
basically stands for "INTEL_CPPC_".

Fine for me, updated it in V7.

Thanks,
Ray