Re: [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider
From: Bjorn Andersson <hidden>
Date: 2021-10-28 23:25:16
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On Thu 21 Oct 03:40 PDT 2021, Odelu Kukatla wrote:
quoted hunk ↗ jump to hunk
Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 SoCs. Signed-off-by: Odelu Kukatla <redacted> --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index d74a4c8..0b55742 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi@@ -3687,6 +3687,14 @@ }; }; + epss_l3: interconnect@18590000 { + compatible = "qcom,sc7280-epss-l3"; + reg = <0 0x18590000 0 0x1000>;
This series looks like I would expect, with and without per-core dcvs. But can you please explain why this contradict what Sibi says here: https://lore.kernel.org/all/1627581885-32165-3-git-send-email-sibis@codeaurora.org/ (local) Regards, Bjorn
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+ #interconnect-cells = <1>;
+ };
+
cpufreq_hw: cpufreq@18591000 {
compatible = "qcom,cpufreq-epss";
reg = <0 0x18591000 0 0x1000>,
--
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