Re: [PATCH 2/4] cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS
From: Stephen Boyd <hidden>
Date: 2021-08-04 19:01:56
Also in:
linux-arm-msm, linux-devicetree, lkml
Quoting Sibi Sankar (2021-07-29 11:04:43)
Qualcomm SoCs (starting with SM8350) support per core voting for L3 cache frequency.
And the L3 cache frequency voting code can't be put into this cpufreq driver?
quoted hunk ↗ jump to hunk
So, re-arrange the cpufreq register offsets to allow access for the L3 interconnect to implement per core control. Also prevent binding breakage caused by register offset shuffling by using the SM8250/SM8350 EPSS compatible. Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node") Signed-off-by: Sibi Sankar <redacted> --- drivers/cpufreq/qcom-cpufreq-hw.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-)diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index f86859bf76f1..74ef3b38343b 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c@@ -28,6 +28,7 @@ struct qcom_cpufreq_soc_data { u32 reg_volt_lut; u32 reg_perf_state; u8 lut_row_size; + bool skip_enable; }; struct qcom_cpufreq_data {@@ -257,19 +258,31 @@ static const struct qcom_cpufreq_soc_data qcom_soc_data = { .reg_volt_lut = 0x114, .reg_perf_state = 0x920, .lut_row_size = 32, + .skip_enable = false, }; static const struct qcom_cpufreq_soc_data epss_soc_data = { + .reg_freq_lut = 0x0, + .reg_volt_lut = 0x100, + .reg_perf_state = 0x220, + .lut_row_size = 4, + .skip_enable = true, +}; + +static const struct qcom_cpufreq_soc_data epss_sm8250_soc_data = { .reg_enable = 0x0, .reg_freq_lut = 0x100, .reg_volt_lut = 0x200, .reg_perf_state = 0x320, .lut_row_size = 4, + .skip_enable = false, }; static const struct of_device_id qcom_cpufreq_hw_match[] = { { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data }, { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data }, + { .compatible = "qcom,sm8250-cpufreq-epss", .data = &epss_sm8250_soc_data }, + { .compatible = "qcom,sm8350-cpufreq-epss", .data = &epss_sm8250_soc_data }, {} }; MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);@@ -334,10 +347,12 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) data->res = res; /* HW should be in enabled state to proceed */
It looks odd that we're no longer making sure that the clk domain is enabled when we probe the driver. Why is that OK?
- if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) {
- dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
- ret = -ENODEV;
- goto error;
+ if (!data->soc_data->skip_enable) {
+ if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) {
+ dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
+ ret = -ENODEV;
+ goto error;
+ }
}