Hi Ryan,
As we already known, STR will let all cores power down after store the
context(GPR, idmap_gpd, sp etc) of primary core in DDR. It is
different between ARMv7 and ARMv8
For ARMv7,
The boot vector can just be located in 0x00000000 or 0xffff0000, which
is chosen by sampling VINITHI domain within PMU register during
bootup. For some SOCs, one of them is used for cold boot while another
is used for recover from STR or CPU IDLE, which is referred as warm
reset. For this scenario, an AON RAM is usually placed in one of the
region mentioned above. Meanwhile, the vendor will place some code
there for bring the core back to the context where it is powered down.

For ARMv8,
All things are covered by PSCI, you can refer the process from ARM's archive.

On 17 February 2016 at 18:06, Oliver Neukum [off-list ref] wrote:

On Wed, 2016-02-17 at 15:19 +0530, Ryan wrote:

quoted

Suspend to ram. I am sorry - I did not provide complete information.

STR on ARM is peculiar. I have no idea.

        Sorry
                Oliver


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