Re: [PATCH v4 14/20] clk: starfive: jh7110-vout: Allow pixel clock rate propagation
From: sashiko-bot@kernel.org
Date: 2026-09-15 15:38:10
Also in:
dri-devel, linux-clk, linux-devicetree
The dc8200_pix0 and dc8200_pix1 MUXes feed the display controller, and the rate they carry is ultimately produced by the HDMI PHY, which registers hdmitx0_pixelclk as a clock provider. Add CLK_SET_RATE_PARENT to both MUXes so a rate requested on them reaches that parent, instead of being clamped to whatever rate the parent already happens to run at. Co-developed-by: Dominique Belhachemi <redacted> Signed-off-by: Dominique Belhachemi <redacted> Reviewed-by: Joshua Peisach <redacted> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
Sashiko has reviewed this patch and found no issues. It looks great! -- Sashiko AI review · https://sashiko.dev/#/patchset/20260915-jh7110-clean-send-v4-0-f0e4fd6f2cc8@samsung.com?part=14 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy