[PATCH v4 3/3] arm64: dts: cix: Add USB3 PHY node for Sky1
From: Hongliang Yang <hidden>
Date: 2026-09-06 03:25:12
Also in:
linux-arm-kernel, linux-devicetree, lkml
Subsystem:
arm/cix soc support, the rest · Maintainers:
Gary Yang, Fugang Duan, Linus Torvalds
Add the USB3 PHY node for the USB4/USB5 controllers on the CIX Sky1 SoC. Enable the PHY and both of its ports on the Radxa Orion O6 board. Signed-off-by: Hongliang Yang <redacted> --- arch/arm64/boot/dts/cix/sky1-orion-o6.dts | 12 +++++++++ arch/arm64/boot/dts/cix/sky1.dtsi | 31 +++++++++++++++++++++++ 2 files changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
index e39c87774c12..b152942aaa60 100644
--- a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
+++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts@@ -117,3 +117,15 @@ &s5_gpio2 { &uart2 { status = "okay"; }; + +&usb3_phy4 { + status = "okay"; + + usb-port@0 { + status = "okay"; + }; + + usb-port@1 { + status = "okay"; + }; +};
diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
index a77c52296ebd..478c726fae96 100644
--- a/arch/arm64/boot/dts/cix/sky1.dtsi
+++ b/arch/arm64/boot/dts/cix/sky1.dtsi@@ -6,6 +6,8 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/cix,sky1.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/reset/cix,sky1-s5-system-control.h> #include "sky1-power.h" / {
@@ -574,6 +576,35 @@ mbox_ap2sfh: mailbox@80a0000 { cix,mbox-dir = "tx"; }; + usb3_phy4: usb-phy@9210000 { + compatible = "cix,sky1-usb3-phy"; + reg = <0x00 0x09210000 0x00 0x40000>; + #address-cells = <1>; + clocks = <&scmi_clk CLK_TREE_USB3A_PHY3_GATE>, + <&scmi_clk CLK_TREE_USB3A_PHY_x2_REF>; + clock-names = "apb", "ref"; + resets = <&s5_syscon SKY1_USBPHY_SS_RST_N>, + <&s5_syscon SKY1_USBPHY_SS_PST_N>; + reset-names = "core", "apb"; + #size-cells = <0>; + + status = "disabled"; + + usb3_phy4_0: usb-port@0 { + reg = <0>; + #phy-cells = <0>; + + status = "disabled"; + }; + + usb3_phy4_1: usb-port@1 { + reg = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + }; + pcie_x8_rc: pcie@a010000 { compatible = "cix,sky1-pcie-host"; reg = <0x00 0x0a010000 0x00 0x10000>,
--
2.54.0
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