On 7/22/26 10:00 PM, Esteban Urrutia via B4 Relay wrote:
Some SoCs such as SAR2130P, SM7550, SM7635 and SM8475 use 4nm-v1 PLLs.
For SM8475, trying to use qmp_v6_dp_serdes_tbl structs (which are for
4nm-v1.1 PLLs) causes link training to fail because of ref clock
differences, which in turn makes these structs differ.
Add structs for v1 PLLs as well.
Taking a look at commit 545069bcf39e ("phy: qualcomm: qmp-combo: add support for SAR2130P")
it would be great if someone could test these changes on a SAR2130P
based device, since qcom,pll-version is also set to 4nm-v1 on this
platform as can be seen in [1].
[1] https://github.com/LineageOS/android_kernel_qcom_sm8450-devicetrees/blob/lineage-20/qcom/display/display/neo-sde.dtsi#L69
Regards,
Esteban
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