On 7/15/25 03:13, Bryan O'Donoghue wrote:

On 14/07/2025 16:30, Vladimir Zapolskiy wrote:

quoted

quoted

I think that is genuinely something we should handle in camss-csid.c
maybe with some meta-data inside of the ports/endpoints..

This is a CSIPHY property, a CSIPHY hardware configuration and a wiring
of sensors to a CSIPHY. Where is the relation to CSID here? There is no.

All the PHY really needs to know is the # of lanes in aggregate, which
physical lanes to map to which logical lanes and the pixel clock.

We should add additional support to the Kernel's D-PHY API parameters
mechanism to support that physical-to-logical mapping but, that's not
required for this series or for any currently know upstream user of CAMSS.

quoted

Please share at least a device tree node description, which supports
a connection of two sensors to a single CSIPHY, like it shall be done
expectedly.

&camss {
      port@0 {
          csiphy0_lanes01_ep: endpoint0 {
              data-lanes = <0 1>;
              remote-endpoint = <&sensor0_ep>;
          };

          csiphy0_lanes23_ep: endpoint0 {
              data-lanes = <2 3>;
              remote-endpoint = <&sensor1_ep>;
          };
       };
};

Don't you understand that this is broken?.. That's no good.

Please listen and reread the messages given to you above, your proposed
"solution" does not support by design a valid hardware setup of two
sensors connected to the same CSIPHY.

I would propose to stop force pushing an uncorrectable dt scheme, it
makes no sense.

-- 
Best wishes,
Vladimir

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