-----Original Message-----
From: Rob Herring <robh@kernel.org>
Sent: 28 June 2025 02:47
To: Shradha Todi <redacted>
Cc: linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;

linux-

samsung-soc@vger.kernel.org; linux-kernel@vger.kernel.org; linux-phy@lists.infradead.org; linux-
fsd@tesla.com; manivannan.sadhasivam@linaro.org; lpieralisi@kernel.org; kw@linux.com;
bhelgaas@google.com; jingoohan1@gmail.com; krzk+dt@kernel.org; conor+dt@kernel.org;
alim.akhtar@samsung.com; vkoul@kernel.org; kishon@kernel.org; arnd@arndb.de;
m.szyprowski@samsung.com; jh80.chung@samsung.com; pankaj.dubey@samsung.com
Subject: Re: [PATCH v2 07/10] dt-bindings: phy: Add PHY bindings support for FSD SoC

On Wed, Jun 25, 2025 at 10:22:26PM +0530, Shradha Todi wrote:

quoted

Document PHY device tree bindings for Tesla FSD SoCs.

Signed-off-by: Shradha Todi <redacted>
---
 .../bindings/phy/samsung,exynos-pcie-phy.yaml | 25 +++++++++++++++++--
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml

b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml

quoted

index 41df8bb08ff7..4dc20156cdde 100644

--- a/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml

@@ -15,10 +15,13 @@ properties:
     const: 0

   compatible:
-    const: samsung,exynos5433-pcie-phy
+    enum:
+      - samsung,exynos5433-pcie-phy
+      - tesla,fsd-pcie-phy

   reg:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2

   samsung,pmu-syscon:
     $ref: /schemas/types.yaml#/definitions/phandle

@@ -30,6 +33,24 @@ properties:
     description: phandle for FSYS sysreg interface, used to control
                  sysreg registers bits for PCIe PHY

+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - tesla,fsd-pcie-phy
+    then:
+      description:
+        The PHY controller nodes are represented in the aliases node
+        using the following format 'pciephy{n}'. Depending on whether
+        n is 0 or 1, the phy init sequence is chosen.

What? Don't make up your own aliases.

If the PHY instances are different, then maybe you need a different
compatible. If this is just selecting the PHY mode, you can do that in
PHY cells as the mode depends on the consumer.

FSD PCIe has 2 instances of PHY. Both are the same HW Samsung
PHYs (Therefore share the same register offsets). But the PHY used here
does not support auto adaptation so we need to tune the PHYs
according to the use case (considering channel loss, etc). This is why we
have 2 different SW PHY initialization sequence depending on the instance
number. Do you think having different compatible (something like
tesla,fsd-pcie-phy0 and tesla,fsd-pcie-phy1) and having phy ID as platform data
is okay in this case? I actually took reference from files like:
drivers/usb/phy/phy-am335x-control.c
drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
who use alias to differentiate between register offsets for instances.

quoted

+      properties:
+        reg:
+          items:
+            - description: PHY
+            - description: PCS

else:
  properties:
    reg:
      maxItems: 1

Will update. Thanks for the review!

quoted

+
 required:
   - "#phy-cells"
   - compatible
--
2.49.0

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