Thread (22 messages) 22 messages, 6 authors, 2024-10-30

Re: [PATCH v7 6/7] PCI: qcom: Disable ASPM L0s and remove BDF2SID mapping config for X1E80100 SoC

From: Manivannan Sadhasivam <hidden>
Date: 2024-10-30 07:19:01
Also in: linux-arm-msm, linux-clk, linux-devicetree, linux-pci, lkml, stable

On Wed, Oct 30, 2024 at 08:15:05AM +0100, Johan Hovold wrote:
On Wed, Oct 30, 2024 at 01:54:59PM +0800, Qiang Yu wrote:
quoted
On 10/24/2024 2:42 PM, Qiang Yu wrote:
quoted
On 10/18/2024 10:06 PM, Johan Hovold wrote:
quoted
quoted
quoted
Also say something about how L0s is broken so that it is more clear what
the effect of this patch is. On sc8280xp enabling L0s lead to
correctable errors for example.
quoted
quoted
Need more time to confirm the exact reason about disabling L0s.
Will update if get any progress
quoted
I confirmed with HW team and SW team. L0s is not supported on X1E80100, 
it is not fully verified. So we don't want to enable it.
Thanks for checking. A word about what can happen if not disabling it
may still be in place (e.g. the link state transition stats in debugfs
on x1e80100 looked pretty erratic with L0s enabled IIRC).

Also, are there any Qualcomm platforms that actually support L0s?
Perhaps we should just disable it everywhere?
Most of the mobile chipsets from Qcom support L0s. It is not supported only on
the compute ones. So we cannot disable it everywhere.

Again, it is not the hw issue but the PHY init sequence not tuned support L0s.

- Mani

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