Re: [PATCH 2/7] phy: qcom-qmp: qserdes-txrx: Add some more v6.20 register offsets
From: Abel Vesa <hidden>
Date: 2023-12-04 11:29:10
Also in:
linux-arm-msm, lkml
On 23-11-22 12:12:00, Dmitry Baryshkov wrote:
On Wed, 22 Nov 2023 at 12:04, Abel Vesa [off-list ref] wrote:quoted
Add some missing v6.20 registers offsets that are needed by the new Snapdragon X Elite (X1E80100) platform. Signed-off-by: Abel Vesa <redacted> --- drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h | 4 ++++ 1 file changed, 4 insertions(+)diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h index 5385a8b60970..7402a94d1be8 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h@@ -14,11 +14,14 @@ #define QSERDES_V6_20_TX_LANE_MODE_3 0x80 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2 0x08 +#define QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2 0x18 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3 0x0cAs a side note, this should be probably 0x1c. Could you please verify it and send a fix?
Double checked. The values are correct. So I'll just put the SO_GAIN_RATE_2 below FO_GAIN_RATE_3.
quoted
#define QSERDES_V6_20_RX_UCDR_PI_CONTROLS 0x20 #define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x34 #define QSERDES_V6_20_RX_IVCM_CAL_CTRL2 0x9c #define QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET 0xa0 +#define QSERDES_V6_20_RX_DFE_1 0xac +#define QSERDES_V6_20_RX_DFE_2 0xb0 #define QSERDES_V6_20_RX_DFE_3 0xb4 #define QSERDES_V6_20_RX_VGA_CAL_MAN_VAL 0xe8 #define QSERDES_V6_20_RX_GM_CAL 0x10c@@ -41,5 +44,6 @@ #define QSERDES_V6_20_RX_MODE_RATE3_B4 0x220 #define QSERDES_V6_20_RX_MODE_RATE3_B5 0x224 #define QSERDES_V6_20_RX_MODE_RATE3_B6 0x228 +#define QSERDES_V6_20_RX_BKUP_CTRL1 0x22c #endif --2.34.1-- With best wishes Dmitry
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