Hi Vinod,

-----Original Message-----
From: Roger Quadros <rogerq@kernel.org>
Sent: Monday, February 20, 2023 9:50 PM
To: Swapnil Kashinath Jakhade <redacted>;
vkoul@kernel.org; kishon@kernel.org; linux-phy@lists.infradead.org; linux-
kernel@vger.kernel.org
Cc: Milind Parab <redacted>
Subject: Re: [PATCH] phy: cadence: Sierra: Add PCIe + SGMII PHY multilink
configuration

EXTERNAL MAIL




On 20/02/2023 16:12, Swapnil Jakhade wrote:

quoted

Add register sequences for PCIe + SGMII PHY multilink configuration.
This has been validated on TI J7 platforms.

Signed-off-by: Swapnil Jakhade <redacted>

Reviewed-by: Roger Quadros <rogerq@kernel.org>

Could you please consider reviewing and merging this patch.

Thanks & regards,
Swapnil
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