Re: [PATCH v3 3/5] dt-binding: Add JH7110 USB wrapper layer doc.
From: Krzysztof Kozlowski <hidden>
Date: 2023-03-17 08:45:37
Also in:
linux-devicetree, linux-riscv, linux-usb, lkml
On 15/03/2023 11:44, Minda Chen wrote:
The dt-binding doc of Cadence USBSS-DRD controller wrapper layer.
Subject: drop full stop. It's not a sentence. Use subject prefixes matching the subsystem (which you can get for example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory your patch is touching).
quoted hunk ↗ jump to hunk
Signed-off-by: Minda Chen <minda.chen@starfivetech.com> --- .../bindings/usb/starfive,jh7110-usb.yaml | 119 ++++++++++++++++++ 1 file changed, 119 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yamldiff --git a/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml new file mode 100644 index 000000000000..b1a8dc6d7b4b --- /dev/null +++ b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml@@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller + +maintainers: + - Minda Chen <minda.chen@starfivetech.com> + +properties: + compatible: + const: starfive,jh7110-usb + + clocks: + items: + - description: lpm clock + - description: stb clock + - description: apb clock + - description: axi clock + - description: utmi apb clock + + clock-names: + items: + - const: lpm + - const: stb + - const: apb + - const: axi + - const: utmi_apb + + resets: + items: + - description: PWRUP reset + - description: APB reset + - description: AXI reset + - description: UTMI_APB reset + + starfive,sys-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle to System Register Controller sys_syscon node. + - description: offset of SYS_SYSCONSAIF__SYSCFG register for USB. + description: + The phandle to System Register Controller syscon node and the offset + of SYS_SYSCONSAIF__SYSCFG register for USB. + + starfive,stg-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle to System Register Controller stg_syscon node. + - description: register0 offset of STG_SYSCONSAIF__SYSCFG register for USB. + - description: register1 offset of STG_SYSCONSAIF__SYSCFG register for USB. + - description: register2 offset of STG_SYSCONSAIF__SYSCFG register for USB. + - description: register3 offset of STG_SYSCONSAIF__SYSCFG register for USB. + description: + The phandle to System Register Controller syscon node and the offset + of STG_SYSCONSAIF__SYSCFG register for USB. Total 4 regsisters offset + for USB. + + "#address-cells": + maximum: 2
enum: [ 1, 2 ] (because 0 should not be valid for you)
+ + "#size-cells": + maximum: 2
ditto
+ + ranges: true + +patternProperties: + "^usb@[0-9a-f]+$": + type: object
missing $ref and unevaluatedProperties: false
+ +required: + - compatible + - clocks + - clock-names + - resets + - starfive,sys-syscon + - starfive,stg-syscon + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false
Best regards, Krzysztof -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy