Hi Johan,

We refer to the IP documents only  and don't notice that the TRM names the registers is different. 

About the SSC, ssc_en = 1， In PCIE mode will set SSC ON, it the same with SATA and USB. 
The document description is not clear enough.

Hi,

See question below.

On 11/14/21 12:40 PM, Johan Jonker wrote:

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Hi Yifeng,

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Some comments. Have a look if it's useful.

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On 10/25/21 10:06 AM, Yifeng Zhao wrote:

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This patch implements a combo phy driver for Rockchip SoCs

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with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy,

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sata-phy or sgmii-phy.

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Signed-off-by: Yifeng Zhao <redacted>

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---

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diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

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+

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+#define BIT_WRITEABLE_SHIFT		16

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+#define REF_CLOCK_24MHz			24000000

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+#define REF_CLOCK_25MHz			25000000

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+#define REF_CLOCK_100MHz		100000000

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+/* RK3568 T22 COMBO PHY REG */

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+#define RK3568_T22_PHYREG5		0x14

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+#define T22_PHYREG5_PLL_DIV_MASK	GENMASK(7, 6)

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+#define T22_PHYREG5_PLL_DIV_SHIFT	6

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+#define T22_PHYREG5_PLL_DIV_2		1

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+

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+#define RK3568_T22_PHYREG6		0x18

Multi-PHY_Register007

Address: Operational Base + offset (0x0018)

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+#define T22_PHYREG6_TX_RTERM_MASK	GENMASK(7, 4)

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+#define T22_PHYREG6_TX_RTERM_SHIFT	4

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+#define T22_PHYREG6_TX_RTERM_50OHM	0x8

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+#define T22_PHYREG6_RX_RTERM_MASK	GENMASK(3, 0)

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+#define T22_PHYREG6_RX_RTERM_SHIFT	0

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+#define T22_PHYREG6_RX_RTERM_44OHM	0xF

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+

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+#define RK3568_T22_PHYREG7		0x1C

Multi-PHY_Register008

Address: Operational Base + offset (0x001C)

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+#define T22_PHYREG7_SSC_EN		BIT(4)

See Rockchip RK3568 TRM Part2 V1.0-20210111 page 1957-1958

It looks as if all PHYREG defines add -1 in value? I'm I correct here?

===

SSC_EN

In U3 and SATA mode, this bit= 1, set SSC on

In PCIE mode, this bit=0 set SSC off

     If Spread Spectrum Clocking (SSC) is used it is

     required that a common reference clock is used by the link partners.

     Most commercially available platforms with PCIe backplanes use

     SSC to reduce EMI.

Maybe a dumb question for in a possible YAML description:

Is this above text from the TRM correct?

Is SSC only used in combination with PCIE instead of U3 and SATA?

===

Johan

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+

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+#define RK3568_T22_PHYREG10		0x28

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+#define T22_PHYREG10_SU_TRIM_0_7	0xF0

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+

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+#define RK3568_T22_PHYREG11		0x2C

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+#define T22_PHYREG11_PLL_LPF_ADJ	0x4

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+

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+#define RK3568_T22_PHYREG12		0x30

Multi-PHY_Register013

Address: Operational Base + offset (0x0030)

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+#define T22_PHYREG12_RESISTER_MASK	GENMASK(5, 4)

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+#define T22_PHYREG12_RESISTER_SHIFT	0x4

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+#define T22_PHYREG12_RESISTER_HIGH_Z	0x3

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+#define T22_PHYREG12_CKRCV_AMP0		BIT(7)

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+

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+#define RK3568_T22_PHYREG13		0x34

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+#define T22_PHYREG13_CKRCV_AMP1		BIT(0)

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+

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+#define RK3568_T22_PHYREG14		0x38

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+#define T22_PHYREG14_CTLE_EN		BIT(0)

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+#define T22_PHYREG14_SSC_CNT_MASK	GENMASK(7, 6)

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+#define T22_PHYREG14_SSC_CNT_SHIFT	6

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+#define T22_PHYREG14_SSC_CNT_VALUE	0x1

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+

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+#define RK3568_T22_PHYREG15		0x3C

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+#define T22_PHYREG15_SSC_CNT_VALUE	0x5f

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+

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+#define RK3568_T22_PHYREG17		0x44

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+#define T22_PHYREG17_PLL_LOOP		0x32

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+

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+#define RK3568_T22_PHYREG31		0x7C

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+#define T22_PHYREG31_SSC_MASK		GENMASK(7, 4)

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+#define T22_PHYREG31_SSC_DIR_SHIFT	4

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+#define T22_PHYREG31_SSC_UPWARD		0

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+#define T22_PHYREG31_SSC_DOWNWARD	1

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+#define T22_PHYREG31_SSC_OFFSET_SHIFT	6

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+#define T22_PHYREG31_SSC_OFFSET_500PPM	1

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+

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+#define RK3568_T22_PHYREG32		0x80

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+#define T22_PHYREG32_PLL_KVCO_MASK	GENMASK(4, 2)

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+#define T22_PHYREG32_PLL_KVCO_SHIFT	2

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+#define T22_PHYREG32_PLL_KVCO_VALUE	2

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+

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