On 17/10/2021 02:09, Bjorn Andersson wrote:

On Sat 16 Oct 11:36 CDT 2021, Dmitry Baryshkov wrote:

quoted

On Sat, 16 Oct 2021 at 01:11, Bjorn Andersson
[off-list ref] wrote:

[..]

quoted

quoted

diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c

[..]

quoted

quoted

+#define QSERDES_COM_SSC_EN_CENTER               0x0010
+#define QSERDES_COM_SSC_ADJ_PER1                0x0014
+#define QSERDES_COM_SSC_PER1                    0x001c
+#define QSERDES_COM_SSC_PER2                    0x0020
+#define QSERDES_COM_SSC_STEP_SIZE1_MODE0        0x0024
+#define QSERDES_COM_SSC_STEP_SIZE2_MODE0        0x0028

I think we might want to use register definitions from phy-qcom-qmp.h,
so that it would be obvious, which generations are handled by the
driver.

I reviewed the all the registers and concluded that the QSERDES is V4,
so I included phy-qcom-qmp.h and used the SERDES_V4 defines instead.

The registers found in the PHY and LANE_TX blocks are specific to this
PHY, so I'm keeping these here.

Yep. They look like V4 DP_PHY registers, but with one extra register 
inserted in the middle.


-- 
With best wishes
Dmitry

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