Hi,
This series adds support for Rx mode on Cadence DPHY driver. It has been
split off from [0] to facilitate easier merging. I have still kept the
version number to maintain continuity with the previous patches. This
series also includes conversion to YAML binding.
Tested on TI's J721E with OV5640 sensor.
[0] https://patchwork.linuxtv.org/project/linux-media/list/?series=5526&state=%2A&archive=both
Changes in v5:
- Based on Laurent's suggestion, add cdns_dphy_info which contains the
phy_ops and cdns_dphy_tx_ops (renamed from cdns_dphy_ops). This lets us
get rid of the phy ops wrappers.
- Move probe() and remove() into cdns_dphy_common_ops() since they can
be used by both modes. Drop the check in power_on().
- Get the clocks in the tx ops probe to make sure they are mandatory for
Tx mode but not for Rx mode.
- Use the new cdns_dphy_info to specify PHY ops.
- Re-order include in alphabetical order.
- Make bands const.
- Drop num_bands.
- Make i, lanes unsigned.
- Drop the maximum check in cdns_dphy_rx_get_band_ctrl(). Let the loop
complete and return -EOPNOTSUPP when we reach the end.
- Drop the "rate < bands[i].min_rate" check since the bands are in
ascending order.
- Move data_lane_ctrl to start of function and make it static const.
- Make clocks a required property based on the compatible.
- Use enum instead.
Changes in v4:
- Instead of having both Rx and Tx modes in the same driver data, keep
them separate since the op selection is based on compatible now. For
that reason, the cdns_dphy_driver_data struct is no longer needed.
- Rename ref_dphy_ops to tx_ref_dphy_ops to clarify their purpose.
- Drop submode checks in validate() hook.
- Drop the submode parts. Use a different compatible for the Rx ops.
- Make bands and num_bands static.
- Drop the submode patches. Use a different compatible for Rx mode DPHY
instead.
Changes in v3:
- Use a table to select the band.
- Use a table to poll the data lane ready bits.
- Multiply the DPHY HS clock rate by 2 to get the bit rate since the
clock is DDR.
- Add Rob's R-by.
Changes in v2:
- Drop reg description.
- Add a description for each DPHY clock.
- Rename dphy@... to phy@... in example.
- Add Laurent's R-by.
- Re-order subject prefixes.
- Re-order subject prefixes.
- Add power-domain to the example.
- Add Laurent's R-by.
- Re-order subject prefixes.
Pratyush Yadav (6):
phy: cdns-dphy: Prepare for Rx support
phy: cdns-dphy: Add Rx support
phy: dt-bindings: Convert Cadence DPHY binding to YAML
phy: dt-bindings: cdns,dphy: make clocks optional for Rx mode
phy: dt-bindings: cdns,dphy: add power-domains property
phy: dt-bindings: cdns,dphy: add Rx DPHY compatible
.../devicetree/bindings/phy/cdns,dphy.txt | 20 -
.../devicetree/bindings/phy/cdns,dphy.yaml | 66 ++++
drivers/phy/cadence/cdns-dphy.c | 351 +++++++++++++++---
3 files changed, 356 insertions(+), 81 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.txt
create mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.yaml
--
2.33.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
The Rx programming sequence differs from the Tx programming sequence.
Currently only Tx mode is supported. For example, the power on and off,
validation, and configuration procedures are all different between Rx
and Tx DPHYs. Currently they are only written from a Tx point of view
and they won't work with an Rx DPHY.
Set the PHY ops from driver data, which makes it possible to use
different PHY callbacks for Rx and Tx modes. Rename cdns_dphy_ops to
cdns_dphy_tx_ops since they are only used by the Tx path. Also move
probe() and remove() to a new struct called cdns_dphy_common_ops. These
can be used by both Rx and Tx paths. cdns_dphy_rx_ops is not added since
it is not needed by the reference Rx mode implementation as of now. It
can be added later if needed.
The clocks "psm" and "pll_ref" are not used by the Rx path so check for
them in the Tx path's probe() callback.
Signed-off-by: Pratyush Yadav <redacted>
---
Changes in v5:
- Based on Laurent's suggestion, add cdns_dphy_info which contains the
phy_ops and cdns_dphy_tx_ops (renamed from cdns_dphy_ops). This lets us
get rid of the phy ops wrappers.
- Move probe() and remove() into cdns_dphy_common_ops() since they can
be used by both modes. Drop the check in power_on().
- Get the clocks in the tx ops probe to make sure they are mandatory for
Tx mode but not for Rx mode.
Changes in v4:
- Instead of having both Rx and Tx modes in the same driver data, keep
them separate since the op selection is based on compatible now. For
that reason, the cdns_dphy_driver_data struct is no longer needed.
- Rename ref_dphy_ops to tx_ref_dphy_ops to clarify their purpose.
- Drop submode checks in validate() hook.
drivers/phy/cadence/cdns-dphy.c | 169 ++++++++++++++++++++------------
1 file changed, 108 insertions(+), 61 deletions(-)
@@ -83,12 +87,21 @@ struct cdns_dphy_ops {unsignedlong(*get_wakeup_time_ns)(structcdns_dphy*dphy);};+structcdns_dphy_info{+conststructphy_ops*phy_ops;+conststructcdns_dphy_common_ops*common_ops;++/* Only set when DPHY is to be used in Tx mode. */+conststructcdns_dphy_tx_ops*tx_ops;+};+structcdns_dphy{structcdns_dphy_cfgcfg;void__iomem*regs;+structdevice*dev;structclk*psm_clk;structclk*pll_ref_clk;-conststructcdns_dphy_ops*ops;+conststructcdns_dphy_info*info;structphy*phy;};
@@ -135,6 +148,7 @@ static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy,staticintcdns_dphy_setup_psm(structcdns_dphy*dphy){+conststructcdns_dphy_tx_ops*ops=dphy->info->tx_ops;unsignedlongpsm_clk_hz=clk_get_rate(dphy->psm_clk);unsignedlongpsm_div;
@@ -142,8 +156,8 @@ static int cdns_dphy_setup_psm(struct cdns_dphy *dphy)return-EINVAL;psm_div=DIV_ROUND_CLOSEST(psm_clk_hz,1000000);-if(dphy->ops->set_psm_div)-dphy->ops->set_psm_div(dphy,psm_div);+if(ops&&ops->set_psm_div)+ops->set_psm_div(dphy,psm_div);return0;}
@@ -151,20 +165,31 @@ static int cdns_dphy_setup_psm(struct cdns_dphy *dphy)staticvoidcdns_dphy_set_clk_lane_cfg(structcdns_dphy*dphy,enumcdns_dphy_clk_lane_cfgcfg){-if(dphy->ops->set_clk_lane_cfg)-dphy->ops->set_clk_lane_cfg(dphy,cfg);+conststructcdns_dphy_tx_ops*ops=dphy->info->tx_ops;++if(ops&&ops->set_clk_lane_cfg)+ops->set_clk_lane_cfg(dphy,cfg);}staticvoidcdns_dphy_set_pll_cfg(structcdns_dphy*dphy,conststructcdns_dphy_cfg*cfg){-if(dphy->ops->set_pll_cfg)-dphy->ops->set_pll_cfg(dphy,cfg);+conststructcdns_dphy_tx_ops*ops=dphy->info->tx_ops;++if(ops&&ops->set_pll_cfg)+ops->set_pll_cfg(dphy,cfg);}staticunsignedlongcdns_dphy_get_wakeup_time_ns(structcdns_dphy*dphy){-returndphy->ops->get_wakeup_time_ns(dphy);+conststructcdns_dphy_tx_ops*ops=dphy->info->tx_ops;++if(!ops||!ops->get_wakeup_time_ns){+dev_err(dphy->dev,"get_wakeup_time_ns() is required\n");+return0;+}++returnops->get_wakeup_time_ns(dphy);}staticunsignedlongcdns_dphy_ref_get_wakeup_time_ns(structcdns_dphy*dphy)
@@ -1,20 +0,0 @@-Cadence DPHY-============--Cadence DPHY block.--Required properties:-- compatible: should be set to "cdns,dphy".-- reg: physical base address and length of the DPHY registers.-- clocks: DPHY reference clocks.-- clock-names: must contain "psm" and "pll_ref".-- #phy-cells: must be set to 0.--Example:- dphy0: dphy@fd0e0000{- compatible = "cdns,dphy";- reg = <0x0 0xfd0e0000 0x0 0x1000>;- clocks = <&psm_clk>, <&pll_ref_clk>;- clock-names = "psm", "pll_ref";- #phy-cells = <0>;- };
The Cadence DPHY can be used to receive image data over the CSI-2
protocol. Add support for Rx mode. The programming sequence differs from
the Tx mode so it is added as a separate set of hooks to isolate the two
paths. The mode in which the DPHY has to be used is selected based on
the compatible.
Signed-off-by: Pratyush Yadav <redacted>
---
Changes in v5:
- Use the new cdns_dphy_info to specify PHY ops.
- Re-order include in alphabetical order.
- Make bands const.
- Drop num_bands.
- Make i, lanes unsigned.
- Drop the maximum check in cdns_dphy_rx_get_band_ctrl(). Let the loop
complete and return -EOPNOTSUPP when we reach the end.
- Drop the "rate < bands[i].min_rate" check since the bands are in
ascending order.
- Move data_lane_ctrl to start of function and make it static const.
Changes in v4:
- Drop the submode parts. Use a different compatible for the Rx ops.
- Make bands and num_bands static.
Changes in v3:
- Use a table to select the band.
- Use a table to poll the data lane ready bits.
- Multiply the DPHY HS clock rate by 2 to get the bit rate since the
clock is DDR.
drivers/phy/cadence/cdns-dphy.c | 182 ++++++++++++++++++++++++++++++++
1 file changed, 182 insertions(+)
@@ -105,6 +132,20 @@ struct cdns_dphy {structphy*phy;};+structcdns_dphy_rx_band{+unsignedintmin_rate;+unsignedintmax_rate;+};++/* Order of bands is important since the index is the band number. */+staticconststructcdns_dphy_rx_bandbands[]={+{80,100},{100,120},{120,160},{160,200},{200,240},+{240,280},{280,320},{320,360},{360,400},{400,480},+{480,560},{560,640},{640,720},{720,800},{800,880},+{880,1040},{1040,1200},{1200,1350},{1350,1500},{1500,1750},+{1750,2000},{2000,2250},{2250,2500}+};+staticintcdns_dsi_get_dphy_pll_cfg(structcdns_dphy*dphy,structcdns_dphy_cfg*cfg,structphy_configure_opts_mipi_dphy*opts,
@@ -360,6 +401,145 @@ static const struct cdns_dphy_info tx_ref_info = {.tx_ops=&tx_ref_dphy_ops,};+staticintcdns_dphy_rx_power_on(structphy*phy)+{+structcdns_dphy*dphy=phy_get_drvdata(phy);++/* Start RX state machine. */+writel(DPHY_CMN_SSM_EN|DPHY_CMN_RX_MODE_EN|+FIELD_PREP(DPHY_CMN_RX_BANDGAP_TIMER_MASK,+DPHY_CMN_RX_BANDGAP_TIMER),+dphy->regs+DPHY_CMN_SSM);++return0;+}++staticintcdns_dphy_rx_power_off(structphy*phy)+{+structcdns_dphy*dphy=phy_get_drvdata(phy);++writel(0,dphy->regs+DPHY_CMN_SSM);++return0;+}++staticintcdns_dphy_rx_get_band_ctrl(unsignedlonghs_clk_rate)+{+unsignedintrate,i;++rate=hs_clk_rate/1000000UL;+/* Since CSI-2 clock is DDR, the bit rate is twice the clock rate. */+rate*=2;++if(rate<bands[0].min_rate)+return-EOPNOTSUPP;++for(i=0;i<ARRAY_SIZE(bands);i++){+if(rate<bands[i].max_rate)+returni;+}++return-EOPNOTSUPP;+}++staticintcdns_dphy_rx_wait_for_bit(void__iomem*addr,unsignedintbit)+{+u32val;++returnreadl_relaxed_poll_timeout(addr,val,val&BIT(bit),10,+DPHY_ISO_LANE_READY_TIMEOUT_MS*1000);+}++staticintcdns_dphy_rx_wait_lane_ready(structcdns_dphy*dphy,+unsignedintlanes)+{+staticconstu32data_lane_ctrl[]={DPHY_ISO_DL_CTRL_L0,+DPHY_ISO_DL_CTRL_L1,+DPHY_ISO_DL_CTRL_L2,+DPHY_ISO_DL_CTRL_L3};+void__iomem*reg=dphy->regs;+unsignedinti;+intret;++/* Data lanes. Minimum one lane is mandatory. */+if(lanes<DPHY_LANES_MIN||lanes>DPHY_LANES_MAX)+return-EINVAL;++/* Clock lane */+ret=cdns_dphy_rx_wait_for_bit(reg+DPHY_ISO_CL_CTRL_L,+DPHY_ISO_LANE_READY_BIT);+if(ret)+returnret;++for(i=0;i<lanes;i++){+ret=cdns_dphy_rx_wait_for_bit(reg+data_lane_ctrl[i],+DPHY_ISO_LANE_READY_BIT);+if(ret)+returnret;+}++return0;+}++staticintcdns_dphy_rx_configure(structphy*phy,+unionphy_configure_opts*opts)+{+structcdns_dphy*dphy=phy_get_drvdata(phy);+unsignedintreg;+intband_ctrl,ret;++band_ctrl=cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate);+if(band_ctrl<0)+returnband_ctrl;++reg=FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND,band_ctrl)|+FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND,band_ctrl);+writel(reg,dphy->regs+DPHY_BAND_CFG);++/*+*Settherequiredpowerislandphase2time.ThisismandatedbyDPHY+*specs.+*/+reg=DPHY_POWER_ISLAND_EN_DATA_VAL;+writel(reg,dphy->regs+DPHY_POWER_ISLAND_EN_DATA);+reg=DPHY_POWER_ISLAND_EN_CLK_VAL;+writel(reg,dphy->regs+DPHY_POWER_ISLAND_EN_CLK);++ret=cdns_dphy_rx_wait_lane_ready(dphy,opts->mipi_dphy.lanes);+if(ret){+dev_err(dphy->dev,"DPHY wait for lane ready timeout\n");+returnret;+}++return0;+}++staticintcdns_dphy_rx_validate(structphy*phy,enumphy_modemode,+intsubmode,unionphy_configure_opts*opts)+{+intret;++if(mode!=PHY_MODE_MIPI_DPHY)+return-EINVAL;++ret=cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate);+if(ret<0)+returnret;++returnphy_mipi_dphy_config_validate(&opts->mipi_dphy);+}++staticconststructphy_opsrx_ref_phy_ops={+.power_on=cdns_dphy_rx_power_on,+.power_off=cdns_dphy_rx_power_off,+.configure=cdns_dphy_rx_configure,+.validate=cdns_dphy_rx_validate,+};++staticconststructcdns_dphy_inforx_ref_info={+.phy_ops=&rx_ref_phy_ops,+};+staticintcdns_dphy_probe(structplatform_device*pdev){structphy_provider*phy_provider;
The clocks are not used by the DPHY when used in Rx mode so make them
optional for it by using a conditional based on compatible.
Signed-off-by: Pratyush Yadav <redacted>
---
Changes in v5:
- Make clocks a required property based on the compatible.
Changes in v3:
- Add Rob's Ack.
Changes in v2:
- Re-order subject prefixes.
.../devicetree/bindings/phy/cdns,dphy.yaml | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
This property is needed on TI platforms to enable the PD of the DPHY
before it can be used.
Signed-off-by: Pratyush Yadav <redacted>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Rob Herring <robh@kernel.org>
---
(no changes since v3)
Changes in v3:
- Add Rob's Ack.
Changes in v2:
- Add power-domain to the example.
- Add Laurent's R-by.
- Re-order subject prefixes.
Documentation/devicetree/bindings/phy/cdns,dphy.yaml | 5 +++++
1 file changed, 5 insertions(+)
The DPHY is treated to be in Tx mode by default. Add a new compatible
for Rx mode DPHYs.
Signed-off-by: Pratyush Yadav <redacted>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
Changes in v5:
- Use enum instead.
- Add Laurent's R-by.
Changes in v4:
- New in v4.
Documentation/devicetree/bindings/phy/cdns,dphy.yaml | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
From: Rob Herring <robh@kernel.org> Date: 2021-09-07 19:02:25
On Fri, 03 Sep 2021 00:25:41 +0530, Pratyush Yadav wrote:
The clocks are not used by the DPHY when used in Rx mode so make them
optional for it by using a conditional based on compatible.
Signed-off-by: Pratyush Yadav <redacted>
---
Changes in v5:
- Make clocks a required property based on the compatible.
Changes in v3:
- Add Rob's Ack.
Changes in v2:
- Re-order subject prefixes.
.../devicetree/bindings/phy/cdns,dphy.yaml | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
From: Rob Herring <robh@kernel.org> Date: 2021-09-07 19:03:58
On Fri, 03 Sep 2021 00:25:43 +0530, Pratyush Yadav wrote:
The DPHY is treated to be in Tx mode by default. Add a new compatible
for Rx mode DPHYs.
Signed-off-by: Pratyush Yadav <redacted>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
Changes in v5:
- Use enum instead.
- Add Laurent's R-by.
Changes in v4:
- New in v4.
Documentation/devicetree/bindings/phy/cdns,dphy.yaml | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
From: Paul Kocialkowski <hidden> Date: 2021-09-16 10:23:04
Hi,
On Fri 03 Sep 21, 00:25, Pratyush Yadav wrote:
The Cadence DPHY can be used to receive image data over the CSI-2
protocol. Add support for Rx mode. The programming sequence differs from
the Tx mode so it is added as a separate set of hooks to isolate the two
paths. The mode in which the DPHY has to be used is selected based on
the compatible.
I just realized that I didn't follow-up on a previous revision on the debate
about using the phy sub-mode to distinguish between rx/tx.
I see that you've been using a dedicated compatible, but I'm not sure this is a
good fit either. My understanding is that the compatible should describe a group
of register-compatible revisions of a hardware component, not how the hardware
is used specifically. I guess the distinction between rx/tx falls under
the latter rather than the former.
I just sent out a patch in my Allwinner MIPI CSI-2+ISP series adding
a specific direction property:
- https://lists.infradead.org/pipermail/linux-phy/2021-September/001420.html
- https://lists.infradead.org/pipermail/linux-phy/2021-September/001421.html
Which I feel is a more appropriate solution to implement the distinction.
What do you think?
Cheers,
Paul
quoted hunk
Signed-off-by: Pratyush Yadav <redacted>
---
Changes in v5:
- Use the new cdns_dphy_info to specify PHY ops.
- Re-order include in alphabetical order.
- Make bands const.
- Drop num_bands.
- Make i, lanes unsigned.
- Drop the maximum check in cdns_dphy_rx_get_band_ctrl(). Let the loop
complete and return -EOPNOTSUPP when we reach the end.
- Drop the "rate < bands[i].min_rate" check since the bands are in
ascending order.
- Move data_lane_ctrl to start of function and make it static const.
Changes in v4:
- Drop the submode parts. Use a different compatible for the Rx ops.
- Make bands and num_bands static.
Changes in v3:
- Use a table to select the band.
- Use a table to poll the data lane ready bits.
- Multiply the DPHY HS clock rate by 2 to get the bit rate since the
clock is DDR.
drivers/phy/cadence/cdns-dphy.c | 182 ++++++++++++++++++++++++++++++++
1 file changed, 182 insertions(+)
@@ -105,6 +132,20 @@ struct cdns_dphy {structphy*phy;};+structcdns_dphy_rx_band{+unsignedintmin_rate;+unsignedintmax_rate;+};++/* Order of bands is important since the index is the band number. */+staticconststructcdns_dphy_rx_bandbands[]={+{80,100},{100,120},{120,160},{160,200},{200,240},+{240,280},{280,320},{320,360},{360,400},{400,480},+{480,560},{560,640},{640,720},{720,800},{800,880},+{880,1040},{1040,1200},{1200,1350},{1350,1500},{1500,1750},+{1750,2000},{2000,2250},{2250,2500}+};+staticintcdns_dsi_get_dphy_pll_cfg(structcdns_dphy*dphy,structcdns_dphy_cfg*cfg,structphy_configure_opts_mipi_dphy*opts,
@@ -360,6 +401,145 @@ static const struct cdns_dphy_info tx_ref_info = {.tx_ops=&tx_ref_dphy_ops,};+staticintcdns_dphy_rx_power_on(structphy*phy)+{+structcdns_dphy*dphy=phy_get_drvdata(phy);++/* Start RX state machine. */+writel(DPHY_CMN_SSM_EN|DPHY_CMN_RX_MODE_EN|+FIELD_PREP(DPHY_CMN_RX_BANDGAP_TIMER_MASK,+DPHY_CMN_RX_BANDGAP_TIMER),+dphy->regs+DPHY_CMN_SSM);++return0;+}++staticintcdns_dphy_rx_power_off(structphy*phy)+{+structcdns_dphy*dphy=phy_get_drvdata(phy);++writel(0,dphy->regs+DPHY_CMN_SSM);++return0;+}++staticintcdns_dphy_rx_get_band_ctrl(unsignedlonghs_clk_rate)+{+unsignedintrate,i;++rate=hs_clk_rate/1000000UL;+/* Since CSI-2 clock is DDR, the bit rate is twice the clock rate. */+rate*=2;++if(rate<bands[0].min_rate)+return-EOPNOTSUPP;++for(i=0;i<ARRAY_SIZE(bands);i++){+if(rate<bands[i].max_rate)+returni;+}++return-EOPNOTSUPP;+}++staticintcdns_dphy_rx_wait_for_bit(void__iomem*addr,unsignedintbit)+{+u32val;++returnreadl_relaxed_poll_timeout(addr,val,val&BIT(bit),10,+DPHY_ISO_LANE_READY_TIMEOUT_MS*1000);+}++staticintcdns_dphy_rx_wait_lane_ready(structcdns_dphy*dphy,+unsignedintlanes)+{+staticconstu32data_lane_ctrl[]={DPHY_ISO_DL_CTRL_L0,+DPHY_ISO_DL_CTRL_L1,+DPHY_ISO_DL_CTRL_L2,+DPHY_ISO_DL_CTRL_L3};+void__iomem*reg=dphy->regs;+unsignedinti;+intret;++/* Data lanes. Minimum one lane is mandatory. */+if(lanes<DPHY_LANES_MIN||lanes>DPHY_LANES_MAX)+return-EINVAL;++/* Clock lane */+ret=cdns_dphy_rx_wait_for_bit(reg+DPHY_ISO_CL_CTRL_L,+DPHY_ISO_LANE_READY_BIT);+if(ret)+returnret;++for(i=0;i<lanes;i++){+ret=cdns_dphy_rx_wait_for_bit(reg+data_lane_ctrl[i],+DPHY_ISO_LANE_READY_BIT);+if(ret)+returnret;+}++return0;+}++staticintcdns_dphy_rx_configure(structphy*phy,+unionphy_configure_opts*opts)+{+structcdns_dphy*dphy=phy_get_drvdata(phy);+unsignedintreg;+intband_ctrl,ret;++band_ctrl=cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate);+if(band_ctrl<0)+returnband_ctrl;++reg=FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND,band_ctrl)|+FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND,band_ctrl);+writel(reg,dphy->regs+DPHY_BAND_CFG);++/*+*Settherequiredpowerislandphase2time.ThisismandatedbyDPHY+*specs.+*/+reg=DPHY_POWER_ISLAND_EN_DATA_VAL;+writel(reg,dphy->regs+DPHY_POWER_ISLAND_EN_DATA);+reg=DPHY_POWER_ISLAND_EN_CLK_VAL;+writel(reg,dphy->regs+DPHY_POWER_ISLAND_EN_CLK);++ret=cdns_dphy_rx_wait_lane_ready(dphy,opts->mipi_dphy.lanes);+if(ret){+dev_err(dphy->dev,"DPHY wait for lane ready timeout\n");+returnret;+}++return0;+}++staticintcdns_dphy_rx_validate(structphy*phy,enumphy_modemode,+intsubmode,unionphy_configure_opts*opts)+{+intret;++if(mode!=PHY_MODE_MIPI_DPHY)+return-EINVAL;++ret=cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate);+if(ret<0)+returnret;++returnphy_mipi_dphy_config_validate(&opts->mipi_dphy);+}++staticconststructphy_opsrx_ref_phy_ops={+.power_on=cdns_dphy_rx_power_on,+.power_off=cdns_dphy_rx_power_off,+.configure=cdns_dphy_rx_configure,+.validate=cdns_dphy_rx_validate,+};++staticconststructcdns_dphy_inforx_ref_info={+.phy_ops=&rx_ref_phy_ops,+};+staticintcdns_dphy_probe(structplatform_device*pdev){structphy_provider*phy_provider;
+Rob
On 16/09/21 12:22PM, Paul Kocialkowski wrote:
Hi,
On Fri 03 Sep 21, 00:25, Pratyush Yadav wrote:
quoted
The Cadence DPHY can be used to receive image data over the CSI-2
protocol. Add support for Rx mode. The programming sequence differs from
the Tx mode so it is added as a separate set of hooks to isolate the two
paths. The mode in which the DPHY has to be used is selected based on
the compatible.
I just realized that I didn't follow-up on a previous revision on the debate
about using the phy sub-mode to distinguish between rx/tx.
I see that you've been using a dedicated compatible, but I'm not sure this is a
good fit either. My understanding is that the compatible should describe a group
of register-compatible revisions of a hardware component, not how the hardware
is used specifically. I guess the distinction between rx/tx falls under
the latter rather than the former.
I am not sure if that is the case. For example, we use "ti,am654-ospi"
for Cadence Quadspi controller. The default compatible, "cdns,qspi-nor",
only supports Quad SPI (4 lines). The "ti,am654-ospi" compatible also
supports Octal SPI (8 lines).
In addition, I feel like the Rx DPHY is almost a different type of
device from a Tx DPHY. The programming sequence is completely different,
the clocks required are different, etc. So I think using a different
compatible for Rx mode makes sense.
Rob, what do you think?
Signed-off-by: Pratyush Yadav <redacted>
---
Changes in v5:
- Use the new cdns_dphy_info to specify PHY ops.
- Re-order include in alphabetical order.
- Make bands const.
- Drop num_bands.
- Make i, lanes unsigned.
- Drop the maximum check in cdns_dphy_rx_get_band_ctrl(). Let the loop
complete and return -EOPNOTSUPP when we reach the end.
- Drop the "rate < bands[i].min_rate" check since the bands are in
ascending order.
- Move data_lane_ctrl to start of function and make it static const.
Changes in v4:
- Drop the submode parts. Use a different compatible for the Rx ops.
- Make bands and num_bands static.
Changes in v3:
- Use a table to select the band.
- Use a table to poll the data lane ready bits.
- Multiply the DPHY HS clock rate by 2 to get the bit rate since the
clock is DDR.
drivers/phy/cadence/cdns-dphy.c | 182 ++++++++++++++++++++++++++++++++
1 file changed, 182 insertions(+)
@@ -105,6 +132,20 @@ struct cdns_dphy {structphy*phy;};+structcdns_dphy_rx_band{+unsignedintmin_rate;+unsignedintmax_rate;+};++/* Order of bands is important since the index is the band number. */+staticconststructcdns_dphy_rx_bandbands[]={+{80,100},{100,120},{120,160},{160,200},{200,240},+{240,280},{280,320},{320,360},{360,400},{400,480},+{480,560},{560,640},{640,720},{720,800},{800,880},+{880,1040},{1040,1200},{1200,1350},{1350,1500},{1500,1750},+{1750,2000},{2000,2250},{2250,2500}+};+staticintcdns_dsi_get_dphy_pll_cfg(structcdns_dphy*dphy,structcdns_dphy_cfg*cfg,structphy_configure_opts_mipi_dphy*opts,
@@ -360,6 +401,145 @@ static const struct cdns_dphy_info tx_ref_info = {.tx_ops=&tx_ref_dphy_ops,};+staticintcdns_dphy_rx_power_on(structphy*phy)+{+structcdns_dphy*dphy=phy_get_drvdata(phy);++/* Start RX state machine. */+writel(DPHY_CMN_SSM_EN|DPHY_CMN_RX_MODE_EN|+FIELD_PREP(DPHY_CMN_RX_BANDGAP_TIMER_MASK,+DPHY_CMN_RX_BANDGAP_TIMER),+dphy->regs+DPHY_CMN_SSM);++return0;+}++staticintcdns_dphy_rx_power_off(structphy*phy)+{+structcdns_dphy*dphy=phy_get_drvdata(phy);++writel(0,dphy->regs+DPHY_CMN_SSM);++return0;+}++staticintcdns_dphy_rx_get_band_ctrl(unsignedlonghs_clk_rate)+{+unsignedintrate,i;++rate=hs_clk_rate/1000000UL;+/* Since CSI-2 clock is DDR, the bit rate is twice the clock rate. */+rate*=2;++if(rate<bands[0].min_rate)+return-EOPNOTSUPP;++for(i=0;i<ARRAY_SIZE(bands);i++){+if(rate<bands[i].max_rate)+returni;+}++return-EOPNOTSUPP;+}++staticintcdns_dphy_rx_wait_for_bit(void__iomem*addr,unsignedintbit)+{+u32val;++returnreadl_relaxed_poll_timeout(addr,val,val&BIT(bit),10,+DPHY_ISO_LANE_READY_TIMEOUT_MS*1000);+}++staticintcdns_dphy_rx_wait_lane_ready(structcdns_dphy*dphy,+unsignedintlanes)+{+staticconstu32data_lane_ctrl[]={DPHY_ISO_DL_CTRL_L0,+DPHY_ISO_DL_CTRL_L1,+DPHY_ISO_DL_CTRL_L2,+DPHY_ISO_DL_CTRL_L3};+void__iomem*reg=dphy->regs;+unsignedinti;+intret;++/* Data lanes. Minimum one lane is mandatory. */+if(lanes<DPHY_LANES_MIN||lanes>DPHY_LANES_MAX)+return-EINVAL;++/* Clock lane */+ret=cdns_dphy_rx_wait_for_bit(reg+DPHY_ISO_CL_CTRL_L,+DPHY_ISO_LANE_READY_BIT);+if(ret)+returnret;++for(i=0;i<lanes;i++){+ret=cdns_dphy_rx_wait_for_bit(reg+data_lane_ctrl[i],+DPHY_ISO_LANE_READY_BIT);+if(ret)+returnret;+}++return0;+}++staticintcdns_dphy_rx_configure(structphy*phy,+unionphy_configure_opts*opts)+{+structcdns_dphy*dphy=phy_get_drvdata(phy);+unsignedintreg;+intband_ctrl,ret;++band_ctrl=cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate);+if(band_ctrl<0)+returnband_ctrl;++reg=FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND,band_ctrl)|+FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND,band_ctrl);+writel(reg,dphy->regs+DPHY_BAND_CFG);++/*+*Settherequiredpowerislandphase2time.ThisismandatedbyDPHY+*specs.+*/+reg=DPHY_POWER_ISLAND_EN_DATA_VAL;+writel(reg,dphy->regs+DPHY_POWER_ISLAND_EN_DATA);+reg=DPHY_POWER_ISLAND_EN_CLK_VAL;+writel(reg,dphy->regs+DPHY_POWER_ISLAND_EN_CLK);++ret=cdns_dphy_rx_wait_lane_ready(dphy,opts->mipi_dphy.lanes);+if(ret){+dev_err(dphy->dev,"DPHY wait for lane ready timeout\n");+returnret;+}++return0;+}++staticintcdns_dphy_rx_validate(structphy*phy,enumphy_modemode,+intsubmode,unionphy_configure_opts*opts)+{+intret;++if(mode!=PHY_MODE_MIPI_DPHY)+return-EINVAL;++ret=cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate);+if(ret<0)+returnret;++returnphy_mipi_dphy_config_validate(&opts->mipi_dphy);+}++staticconststructphy_opsrx_ref_phy_ops={+.power_on=cdns_dphy_rx_power_on,+.power_off=cdns_dphy_rx_power_off,+.configure=cdns_dphy_rx_configure,+.validate=cdns_dphy_rx_validate,+};++staticconststructcdns_dphy_inforx_ref_info={+.phy_ops=&rx_ref_phy_ops,+};+staticintcdns_dphy_probe(structplatform_device*pdev){structphy_provider*phy_provider;
+Rob
On 16/09/21 12:22PM, Paul Kocialkowski wrote:
quoted
Hi,
On Fri 03 Sep 21, 00:25, Pratyush Yadav wrote:
quoted
The Cadence DPHY can be used to receive image data over the CSI-2
protocol. Add support for Rx mode. The programming sequence differs from
the Tx mode so it is added as a separate set of hooks to isolate the two
paths. The mode in which the DPHY has to be used is selected based on
the compatible.
I just realized that I didn't follow-up on a previous revision on the debate
about using the phy sub-mode to distinguish between rx/tx.
I see that you've been using a dedicated compatible, but I'm not sure this is a
good fit either. My understanding is that the compatible should describe a group
of register-compatible revisions of a hardware component, not how the hardware
is used specifically. I guess the distinction between rx/tx falls under
the latter rather than the former.
I am not sure if that is the case. For example, we use "ti,am654-ospi"
for Cadence Quadspi controller. The default compatible, "cdns,qspi-nor",
only supports Quad SPI (4 lines). The "ti,am654-ospi" compatible also
supports Octal SPI (8 lines).
In addition, I feel like the Rx DPHY is almost a different type of
device from a Tx DPHY. The programming sequence is completely different,
the clocks required are different, etc. So I think using a different
compatible for Rx mode makes sense.
Rob, what do you think?
Ping. I think my current approach works well. Unless there are any
objections I would like this series to move forward please.
Signed-off-by: Pratyush Yadav <redacted>
---
Changes in v5:
- Use the new cdns_dphy_info to specify PHY ops.
- Re-order include in alphabetical order.
- Make bands const.
- Drop num_bands.
- Make i, lanes unsigned.
- Drop the maximum check in cdns_dphy_rx_get_band_ctrl(). Let the loop
complete and return -EOPNOTSUPP when we reach the end.
- Drop the "rate < bands[i].min_rate" check since the bands are in
ascending order.
- Move data_lane_ctrl to start of function and make it static const.
Changes in v4:
- Drop the submode parts. Use a different compatible for the Rx ops.
- Make bands and num_bands static.
Changes in v3:
- Use a table to select the band.
- Use a table to poll the data lane ready bits.
- Multiply the DPHY HS clock rate by 2 to get the bit rate since the
clock is DDR.
drivers/phy/cadence/cdns-dphy.c | 182 ++++++++++++++++++++++++++++++++
1 file changed, 182 insertions(+)
@@ -105,6 +132,20 @@ struct cdns_dphy {structphy*phy;};+structcdns_dphy_rx_band{+unsignedintmin_rate;+unsignedintmax_rate;+};++/* Order of bands is important since the index is the band number. */+staticconststructcdns_dphy_rx_bandbands[]={+{80,100},{100,120},{120,160},{160,200},{200,240},+{240,280},{280,320},{320,360},{360,400},{400,480},+{480,560},{560,640},{640,720},{720,800},{800,880},+{880,1040},{1040,1200},{1200,1350},{1350,1500},{1500,1750},+{1750,2000},{2000,2250},{2250,2500}+};+staticintcdns_dsi_get_dphy_pll_cfg(structcdns_dphy*dphy,structcdns_dphy_cfg*cfg,structphy_configure_opts_mipi_dphy*opts,
@@ -360,6 +401,145 @@ static const struct cdns_dphy_info tx_ref_info = {.tx_ops=&tx_ref_dphy_ops,};+staticintcdns_dphy_rx_power_on(structphy*phy)+{+structcdns_dphy*dphy=phy_get_drvdata(phy);++/* Start RX state machine. */+writel(DPHY_CMN_SSM_EN|DPHY_CMN_RX_MODE_EN|+FIELD_PREP(DPHY_CMN_RX_BANDGAP_TIMER_MASK,+DPHY_CMN_RX_BANDGAP_TIMER),+dphy->regs+DPHY_CMN_SSM);++return0;+}++staticintcdns_dphy_rx_power_off(structphy*phy)+{+structcdns_dphy*dphy=phy_get_drvdata(phy);++writel(0,dphy->regs+DPHY_CMN_SSM);++return0;+}++staticintcdns_dphy_rx_get_band_ctrl(unsignedlonghs_clk_rate)+{+unsignedintrate,i;++rate=hs_clk_rate/1000000UL;+/* Since CSI-2 clock is DDR, the bit rate is twice the clock rate. */+rate*=2;++if(rate<bands[0].min_rate)+return-EOPNOTSUPP;++for(i=0;i<ARRAY_SIZE(bands);i++){+if(rate<bands[i].max_rate)+returni;+}++return-EOPNOTSUPP;+}++staticintcdns_dphy_rx_wait_for_bit(void__iomem*addr,unsignedintbit)+{+u32val;++returnreadl_relaxed_poll_timeout(addr,val,val&BIT(bit),10,+DPHY_ISO_LANE_READY_TIMEOUT_MS*1000);+}++staticintcdns_dphy_rx_wait_lane_ready(structcdns_dphy*dphy,+unsignedintlanes)+{+staticconstu32data_lane_ctrl[]={DPHY_ISO_DL_CTRL_L0,+DPHY_ISO_DL_CTRL_L1,+DPHY_ISO_DL_CTRL_L2,+DPHY_ISO_DL_CTRL_L3};+void__iomem*reg=dphy->regs;+unsignedinti;+intret;++/* Data lanes. Minimum one lane is mandatory. */+if(lanes<DPHY_LANES_MIN||lanes>DPHY_LANES_MAX)+return-EINVAL;++/* Clock lane */+ret=cdns_dphy_rx_wait_for_bit(reg+DPHY_ISO_CL_CTRL_L,+DPHY_ISO_LANE_READY_BIT);+if(ret)+returnret;++for(i=0;i<lanes;i++){+ret=cdns_dphy_rx_wait_for_bit(reg+data_lane_ctrl[i],+DPHY_ISO_LANE_READY_BIT);+if(ret)+returnret;+}++return0;+}++staticintcdns_dphy_rx_configure(structphy*phy,+unionphy_configure_opts*opts)+{+structcdns_dphy*dphy=phy_get_drvdata(phy);+unsignedintreg;+intband_ctrl,ret;++band_ctrl=cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate);+if(band_ctrl<0)+returnband_ctrl;++reg=FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND,band_ctrl)|+FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND,band_ctrl);+writel(reg,dphy->regs+DPHY_BAND_CFG);++/*+*Settherequiredpowerislandphase2time.ThisismandatedbyDPHY+*specs.+*/+reg=DPHY_POWER_ISLAND_EN_DATA_VAL;+writel(reg,dphy->regs+DPHY_POWER_ISLAND_EN_DATA);+reg=DPHY_POWER_ISLAND_EN_CLK_VAL;+writel(reg,dphy->regs+DPHY_POWER_ISLAND_EN_CLK);++ret=cdns_dphy_rx_wait_lane_ready(dphy,opts->mipi_dphy.lanes);+if(ret){+dev_err(dphy->dev,"DPHY wait for lane ready timeout\n");+returnret;+}++return0;+}++staticintcdns_dphy_rx_validate(structphy*phy,enumphy_modemode,+intsubmode,unionphy_configure_opts*opts)+{+intret;++if(mode!=PHY_MODE_MIPI_DPHY)+return-EINVAL;++ret=cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate);+if(ret<0)+returnret;++returnphy_mipi_dphy_config_validate(&opts->mipi_dphy);+}++staticconststructphy_opsrx_ref_phy_ops={+.power_on=cdns_dphy_rx_power_on,+.power_off=cdns_dphy_rx_power_off,+.configure=cdns_dphy_rx_configure,+.validate=cdns_dphy_rx_validate,+};++staticconststructcdns_dphy_inforx_ref_info={+.phy_ops=&rx_ref_phy_ops,+};+staticintcdns_dphy_probe(structplatform_device*pdev){structphy_provider*phy_provider;
Hi Pratyush,
On 17-09-21, 22:58, Pratyush Yadav wrote:
+Rob
On 16/09/21 12:22PM, Paul Kocialkowski wrote:
quoted
Hi,
On Fri 03 Sep 21, 00:25, Pratyush Yadav wrote:
quoted
The Cadence DPHY can be used to receive image data over the CSI-2
protocol. Add support for Rx mode. The programming sequence differs from
the Tx mode so it is added as a separate set of hooks to isolate the two
paths. The mode in which the DPHY has to be used is selected based on
the compatible.
I just realized that I didn't follow-up on a previous revision on the debate
about using the phy sub-mode to distinguish between rx/tx.
I see that you've been using a dedicated compatible, but I'm not sure this is a
good fit either. My understanding is that the compatible should describe a group
of register-compatible revisions of a hardware component, not how the hardware
is used specifically. I guess the distinction between rx/tx falls under
the latter rather than the former.
I am not sure if that is the case. For example, we use "ti,am654-ospi"
for Cadence Quadspi controller. The default compatible, "cdns,qspi-nor",
only supports Quad SPI (4 lines). The "ti,am654-ospi" compatible also
supports Octal SPI (8 lines).
Those are hardware defaults right?
In addition, I feel like the Rx DPHY is almost a different type of
device from a Tx DPHY. The programming sequence is completely different,
Is that due to direction or something else..?
the clocks required are different, etc. So I think using a different
compatible for Rx mode makes sense.
Is the underlaying IP not capable of both TX and RX and in the specific
situations you are using it as TX and RX.
I am okay that default being TX but you can use Paul's approach of
direction with this to make it better proposal
--
~Vinod
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
Hi Pratyush,
On 17-09-21, 22:58, Pratyush Yadav wrote:
quoted
+Rob
On 16/09/21 12:22PM, Paul Kocialkowski wrote:
quoted
Hi,
On Fri 03 Sep 21, 00:25, Pratyush Yadav wrote:
quoted
The Cadence DPHY can be used to receive image data over the CSI-2
protocol. Add support for Rx mode. The programming sequence differs from
the Tx mode so it is added as a separate set of hooks to isolate the two
paths. The mode in which the DPHY has to be used is selected based on
the compatible.
I just realized that I didn't follow-up on a previous revision on the debate
about using the phy sub-mode to distinguish between rx/tx.
I see that you've been using a dedicated compatible, but I'm not sure this is a
good fit either. My understanding is that the compatible should describe a group
of register-compatible revisions of a hardware component, not how the hardware
is used specifically. I guess the distinction between rx/tx falls under
the latter rather than the former.
I am not sure if that is the case. For example, we use "ti,am654-ospi"
for Cadence Quadspi controller. The default compatible, "cdns,qspi-nor",
only supports Quad SPI (4 lines). The "ti,am654-ospi" compatible also
supports Octal SPI (8 lines).
Those are hardware defaults right?
quoted
In addition, I feel like the Rx DPHY is almost a different type of
device from a Tx DPHY. The programming sequence is completely different,
Is that due to direction or something else..?
Yes, it is due to direction. Different settings need to be applied for
Rx mode.
quoted
the clocks required are different, etc. So I think using a different
compatible for Rx mode makes sense.
Is the underlaying IP not capable of both TX and RX and in the specific
situations you are using it as TX and RX.
Any instance of the underlying IP can only either be TX or RX, it can't
do both.
I am okay that default being TX but you can use Paul's approach of
direction with this to make it better proposal
Hi Pratyush,
Thank you for the patch.
On Fri, Sep 03, 2021 at 12:25:41AM +0530, Pratyush Yadav wrote:
The clocks are not used by the DPHY when used in Rx mode so make them
optional for it by using a conditional based on compatible.
Signed-off-by: Pratyush Yadav <redacted>
---
Changes in v5:
- Make clocks a required property based on the compatible.
Changes in v3:
- Add Rob's Ack.
Changes in v2:
- Re-order subject prefixes.
.../devicetree/bindings/phy/cdns,dphy.yaml | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
Hi Pratyush,
Thank you for the patch.
On Fri, Sep 03, 2021 at 12:25:38AM +0530, Pratyush Yadav wrote:
The Rx programming sequence differs from the Tx programming sequence.
Currently only Tx mode is supported. For example, the power on and off,
validation, and configuration procedures are all different between Rx
and Tx DPHYs. Currently they are only written from a Tx point of view
and they won't work with an Rx DPHY.
Set the PHY ops from driver data, which makes it possible to use
different PHY callbacks for Rx and Tx modes. Rename cdns_dphy_ops to
cdns_dphy_tx_ops since they are only used by the Tx path. Also move
probe() and remove() to a new struct called cdns_dphy_common_ops. These
can be used by both Rx and Tx paths. cdns_dphy_rx_ops is not added since
it is not needed by the reference Rx mode implementation as of now. It
can be added later if needed.
The clocks "psm" and "pll_ref" are not used by the Rx path so check for
them in the Tx path's probe() callback.
Signed-off-by: Pratyush Yadav <redacted>
---
Changes in v5:
- Based on Laurent's suggestion, add cdns_dphy_info which contains the
phy_ops and cdns_dphy_tx_ops (renamed from cdns_dphy_ops). This lets us
get rid of the phy ops wrappers.
- Move probe() and remove() into cdns_dphy_common_ops() since they can
be used by both modes. Drop the check in power_on().
- Get the clocks in the tx ops probe to make sure they are mandatory for
Tx mode but not for Rx mode.
Changes in v4:
- Instead of having both Rx and Tx modes in the same driver data, keep
them separate since the op selection is based on compatible now. For
that reason, the cdns_dphy_driver_data struct is no longer needed.
- Rename ref_dphy_ops to tx_ref_dphy_ops to clarify their purpose.
- Drop submode checks in validate() hook.
drivers/phy/cadence/cdns-dphy.c | 169 ++++++++++++++++++++------------
1 file changed, 108 insertions(+), 61 deletions(-)
@@ -83,12 +87,21 @@ struct cdns_dphy_ops {unsignedlong(*get_wakeup_time_ns)(structcdns_dphy*dphy);};+structcdns_dphy_info{+conststructphy_ops*phy_ops;+conststructcdns_dphy_common_ops*common_ops;++/* Only set when DPHY is to be used in Tx mode. */+conststructcdns_dphy_tx_ops*tx_ops;+};+structcdns_dphy{structcdns_dphy_cfgcfg;void__iomem*regs;+structdevice*dev;structclk*psm_clk;structclk*pll_ref_clk;-conststructcdns_dphy_ops*ops;+conststructcdns_dphy_info*info;structphy*phy;};
@@ -135,6 +148,7 @@ static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy,staticintcdns_dphy_setup_psm(structcdns_dphy*dphy){+conststructcdns_dphy_tx_ops*ops=dphy->info->tx_ops;unsignedlongpsm_clk_hz=clk_get_rate(dphy->psm_clk);unsignedlongpsm_div;
@@ -142,8 +156,8 @@ static int cdns_dphy_setup_psm(struct cdns_dphy *dphy)return-EINVAL;psm_div=DIV_ROUND_CLOSEST(psm_clk_hz,1000000);-if(dphy->ops->set_psm_div)-dphy->ops->set_psm_div(dphy,psm_div);+if(ops&&ops->set_psm_div)+ops->set_psm_div(dphy,psm_div);return0;}
@@ -151,20 +165,31 @@ static int cdns_dphy_setup_psm(struct cdns_dphy *dphy)staticvoidcdns_dphy_set_clk_lane_cfg(structcdns_dphy*dphy,enumcdns_dphy_clk_lane_cfgcfg){-if(dphy->ops->set_clk_lane_cfg)-dphy->ops->set_clk_lane_cfg(dphy,cfg);+conststructcdns_dphy_tx_ops*ops=dphy->info->tx_ops;++if(ops&&ops->set_clk_lane_cfg)+ops->set_clk_lane_cfg(dphy,cfg);}staticvoidcdns_dphy_set_pll_cfg(structcdns_dphy*dphy,conststructcdns_dphy_cfg*cfg){-if(dphy->ops->set_pll_cfg)-dphy->ops->set_pll_cfg(dphy,cfg);+conststructcdns_dphy_tx_ops*ops=dphy->info->tx_ops;++if(ops&&ops->set_pll_cfg)+ops->set_pll_cfg(dphy,cfg);}staticunsignedlongcdns_dphy_get_wakeup_time_ns(structcdns_dphy*dphy){-returndphy->ops->get_wakeup_time_ns(dphy);+conststructcdns_dphy_tx_ops*ops=dphy->info->tx_ops;++if(!ops||!ops->get_wakeup_time_ns){+dev_err(dphy->dev,"get_wakeup_time_ns() is required\n");+return0;+}++returnops->get_wakeup_time_ns(dphy);}staticunsignedlongcdns_dphy_ref_get_wakeup_time_ns(structcdns_dphy*dphy)
Hi Vinod,
On Fri, Oct 01, 2021 at 11:53:16AM +0530, Vinod Koul wrote:
On 17-09-21, 22:58, Pratyush Yadav wrote:
quoted
On 16/09/21 12:22PM, Paul Kocialkowski wrote:
quoted
On Fri 03 Sep 21, 00:25, Pratyush Yadav wrote:
quoted
The Cadence DPHY can be used to receive image data over the CSI-2
protocol. Add support for Rx mode. The programming sequence differs from
the Tx mode so it is added as a separate set of hooks to isolate the two
paths. The mode in which the DPHY has to be used is selected based on
the compatible.
I just realized that I didn't follow-up on a previous revision on the debate
about using the phy sub-mode to distinguish between rx/tx.
I see that you've been using a dedicated compatible, but I'm not sure this is a
good fit either. My understanding is that the compatible should describe a group
of register-compatible revisions of a hardware component, not how the hardware
is used specifically. I guess the distinction between rx/tx falls under
the latter rather than the former.
I am not sure if that is the case. For example, we use "ti,am654-ospi"
for Cadence Quadspi controller. The default compatible, "cdns,qspi-nor",
only supports Quad SPI (4 lines). The "ti,am654-ospi" compatible also
supports Octal SPI (8 lines).
Those are hardware defaults right?
quoted
In addition, I feel like the Rx DPHY is almost a different type of
device from a Tx DPHY. The programming sequence is completely different,
Is that due to direction or something else..?
quoted
the clocks required are different, etc. So I think using a different
compatible for Rx mode makes sense.
Is the underlaying IP not capable of both TX and RX and in the specific
situations you are using it as TX and RX.
I am okay that default being TX but you can use Paul's approach of
direction with this to make it better proposal
Given that the RX and TX implementations are very different (it's not a
matter of selecting a mode at runtime), I'm actually tempted to
recommend having two drivers, one for the RX PHY and one for the TX PHY.
This can only be done with two different compatible strings, which I
think would be a better approach.
It's unfortunate that the original compatible string didn't contain
"tx". We could rename it and keep the old one in the driver for backward
compatibility, making things cleaner going forward.
--
Regards,
Laurent Pinchart
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Hi Vinod,
On Fri, Oct 01, 2021 at 11:53:16AM +0530, Vinod Koul wrote:
quoted
On 17-09-21, 22:58, Pratyush Yadav wrote:
quoted
On 16/09/21 12:22PM, Paul Kocialkowski wrote:
quoted
On Fri 03 Sep 21, 00:25, Pratyush Yadav wrote:
quoted
The Cadence DPHY can be used to receive image data over the CSI-2
protocol. Add support for Rx mode. The programming sequence differs from
the Tx mode so it is added as a separate set of hooks to isolate the two
paths. The mode in which the DPHY has to be used is selected based on
the compatible.
I just realized that I didn't follow-up on a previous revision on the debate
about using the phy sub-mode to distinguish between rx/tx.
I see that you've been using a dedicated compatible, but I'm not sure this is a
good fit either. My understanding is that the compatible should describe a group
of register-compatible revisions of a hardware component, not how the hardware
is used specifically. I guess the distinction between rx/tx falls under
the latter rather than the former.
I am not sure if that is the case. For example, we use "ti,am654-ospi"
for Cadence Quadspi controller. The default compatible, "cdns,qspi-nor",
only supports Quad SPI (4 lines). The "ti,am654-ospi" compatible also
supports Octal SPI (8 lines).
Those are hardware defaults right?
quoted
In addition, I feel like the Rx DPHY is almost a different type of
device from a Tx DPHY. The programming sequence is completely different,
Is that due to direction or something else..?
quoted
the clocks required are different, etc. So I think using a different
compatible for Rx mode makes sense.
Is the underlaying IP not capable of both TX and RX and in the specific
situations you are using it as TX and RX.
I am okay that default being TX but you can use Paul's approach of
direction with this to make it better proposal
Given that the RX and TX implementations are very different (it's not a
matter of selecting a mode at runtime), I'm actually tempted to
recommend having two drivers, one for the RX PHY and one for the TX PHY.
This can only be done with two different compatible strings, which I
think would be a better approach.
FWIW, I think having different drivers would certainly make things
easier to maintain.
It's unfortunate that the original compatible string didn't contain
"tx". We could rename it and keep the old one in the driver for backward
compatibility, making things cleaner going forward.
--
Regards,
Laurent Pinchart
Hi Pratyush,
On Thu, Oct 07, 2021 at 05:44:38PM +0530, Pratyush Yadav wrote:
On 07/10/21 03:10AM, Laurent Pinchart wrote:
quoted
On Fri, Oct 01, 2021 at 11:53:16AM +0530, Vinod Koul wrote:
quoted
On 17-09-21, 22:58, Pratyush Yadav wrote:
quoted
On 16/09/21 12:22PM, Paul Kocialkowski wrote:
quoted
On Fri 03 Sep 21, 00:25, Pratyush Yadav wrote:
quoted
The Cadence DPHY can be used to receive image data over the CSI-2
protocol. Add support for Rx mode. The programming sequence differs from
the Tx mode so it is added as a separate set of hooks to isolate the two
paths. The mode in which the DPHY has to be used is selected based on
the compatible.
I just realized that I didn't follow-up on a previous revision on the debate
about using the phy sub-mode to distinguish between rx/tx.
I see that you've been using a dedicated compatible, but I'm not sure this is a
good fit either. My understanding is that the compatible should describe a group
of register-compatible revisions of a hardware component, not how the hardware
is used specifically. I guess the distinction between rx/tx falls under
the latter rather than the former.
I am not sure if that is the case. For example, we use "ti,am654-ospi"
for Cadence Quadspi controller. The default compatible, "cdns,qspi-nor",
only supports Quad SPI (4 lines). The "ti,am654-ospi" compatible also
supports Octal SPI (8 lines).
Those are hardware defaults right?
quoted
In addition, I feel like the Rx DPHY is almost a different type of
device from a Tx DPHY. The programming sequence is completely different,
Is that due to direction or something else..?
quoted
the clocks required are different, etc. So I think using a different
compatible for Rx mode makes sense.
Is the underlaying IP not capable of both TX and RX and in the specific
situations you are using it as TX and RX.
I am okay that default being TX but you can use Paul's approach of
direction with this to make it better proposal
Given that the RX and TX implementations are very different (it's not a
matter of selecting a mode at runtime), I'm actually tempted to
recommend having two drivers, one for the RX PHY and one for the TX PHY.
This can only be done with two different compatible strings, which I
think would be a better approach.
FWIW, I think having different drivers would certainly make things
easier to maintain.
I'm sorry for not having recommended this in the first place.
Any objection from anyone against going in this direction ?
quoted
It's unfortunate that the original compatible string didn't contain
"tx". We could rename it and keep the old one in the driver for backward
compatibility, making things cleaner going forward.
From: Paul Kocialkowski <hidden> Date: 2021-10-08 12:56:00
Hi,
On Fri 08 Oct 21, 13:27, Laurent Pinchart wrote:
Hi Pratyush,
On Thu, Oct 07, 2021 at 05:44:38PM +0530, Pratyush Yadav wrote:
quoted
On 07/10/21 03:10AM, Laurent Pinchart wrote:
quoted
On Fri, Oct 01, 2021 at 11:53:16AM +0530, Vinod Koul wrote:
quoted
On 17-09-21, 22:58, Pratyush Yadav wrote:
quoted
On 16/09/21 12:22PM, Paul Kocialkowski wrote:
quoted
On Fri 03 Sep 21, 00:25, Pratyush Yadav wrote:
quoted
The Cadence DPHY can be used to receive image data over the CSI-2
protocol. Add support for Rx mode. The programming sequence differs from
the Tx mode so it is added as a separate set of hooks to isolate the two
paths. The mode in which the DPHY has to be used is selected based on
the compatible.
I just realized that I didn't follow-up on a previous revision on the debate
about using the phy sub-mode to distinguish between rx/tx.
I see that you've been using a dedicated compatible, but I'm not sure this is a
good fit either. My understanding is that the compatible should describe a group
of register-compatible revisions of a hardware component, not how the hardware
is used specifically. I guess the distinction between rx/tx falls under
the latter rather than the former.
I am not sure if that is the case. For example, we use "ti,am654-ospi"
for Cadence Quadspi controller. The default compatible, "cdns,qspi-nor",
only supports Quad SPI (4 lines). The "ti,am654-ospi" compatible also
supports Octal SPI (8 lines).
Those are hardware defaults right?
quoted
In addition, I feel like the Rx DPHY is almost a different type of
device from a Tx DPHY. The programming sequence is completely different,
Is that due to direction or something else..?
quoted
the clocks required are different, etc. So I think using a different
compatible for Rx mode makes sense.
Is the underlaying IP not capable of both TX and RX and in the specific
situations you are using it as TX and RX.
I am okay that default being TX but you can use Paul's approach of
direction with this to make it better proposal
Given that the RX and TX implementations are very different (it's not a
matter of selecting a mode at runtime), I'm actually tempted to
recommend having two drivers, one for the RX PHY and one for the TX PHY.
This can only be done with two different compatible strings, which I
think would be a better approach.
FWIW, I think having different drivers would certainly make things
easier to maintain.
I'm sorry for not having recommended this in the first place.
Any objection from anyone against going in this direction ?
So apparently there is not a single register that is shared between rx and tx
and clocks are not the same either so it feels to me like a separate driver
would be legit. This looks like two distinct IPs sharing the same base address.
Cheers,
Paul
quoted
quoted
It's unfortunate that the original compatible string didn't contain
"tx". We could rename it and keep the old one in the driver for backward
compatibility, making things cleaner going forward.
--
Regards,
Laurent Pinchart
--
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
Hi,
On Fri 08 Oct 21, 13:27, Laurent Pinchart wrote:
quoted
Hi Pratyush,
On Thu, Oct 07, 2021 at 05:44:38PM +0530, Pratyush Yadav wrote:
quoted
On 07/10/21 03:10AM, Laurent Pinchart wrote:
quoted
On Fri, Oct 01, 2021 at 11:53:16AM +0530, Vinod Koul wrote:
quoted
On 17-09-21, 22:58, Pratyush Yadav wrote:
quoted
On 16/09/21 12:22PM, Paul Kocialkowski wrote:
quoted
On Fri 03 Sep 21, 00:25, Pratyush Yadav wrote:
quoted
The Cadence DPHY can be used to receive image data over the CSI-2
protocol. Add support for Rx mode. The programming sequence differs from
the Tx mode so it is added as a separate set of hooks to isolate the two
paths. The mode in which the DPHY has to be used is selected based on
the compatible.
I just realized that I didn't follow-up on a previous revision on the debate
about using the phy sub-mode to distinguish between rx/tx.
I see that you've been using a dedicated compatible, but I'm not sure this is a
good fit either. My understanding is that the compatible should describe a group
of register-compatible revisions of a hardware component, not how the hardware
is used specifically. I guess the distinction between rx/tx falls under
the latter rather than the former.
I am not sure if that is the case. For example, we use "ti,am654-ospi"
for Cadence Quadspi controller. The default compatible, "cdns,qspi-nor",
only supports Quad SPI (4 lines). The "ti,am654-ospi" compatible also
supports Octal SPI (8 lines).
Those are hardware defaults right?
quoted
In addition, I feel like the Rx DPHY is almost a different type of
device from a Tx DPHY. The programming sequence is completely different,
Is that due to direction or something else..?
quoted
the clocks required are different, etc. So I think using a different
compatible for Rx mode makes sense.
Is the underlaying IP not capable of both TX and RX and in the specific
situations you are using it as TX and RX.
I am okay that default being TX but you can use Paul's approach of
direction with this to make it better proposal
Given that the RX and TX implementations are very different (it's not a
matter of selecting a mode at runtime), I'm actually tempted to
recommend having two drivers, one for the RX PHY and one for the TX PHY.
This can only be done with two different compatible strings, which I
think would be a better approach.
FWIW, I think having different drivers would certainly make things
easier to maintain.
I'm sorry for not having recommended this in the first place.
Any objection from anyone against going in this direction ?
So apparently there is not a single register that is shared between rx and tx
and clocks are not the same either so it feels to me like a separate driver
would be legit. This looks like two distinct IPs sharing the same base address.