Hi Laurent,

On Mon, Jun 21, 2021 at 11:26 PM Laurent Pinchart
[off-list ref] wrote:

Hi Jagan,

Thank you for the patch.

On Mon, Jun 21, 2021 at 12:54:16PM +0530, Jagan Teki wrote:

quoted

Samsung SEC MIPI DSIM Bridge controller is MIPI DSI bridge
available in NXP's i.MX8M Mini and Nano Processors.

Add dt-bingings for it.

Cc: Andrzej Hajda <redacted>
Cc: Neil Armstrong <redacted>
Cc: Robert Foss <redacted>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 .../display/bridge/samsung,sec-dsim.yaml      | 184 ++++++++++++++++++
 1 file changed, 184 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.yaml
new file mode 100644
index 000000000000..32f67f313dfd
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/samsung,sec-dsim.yaml

@@ -0,0 +1,184 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/samsung,sec-dsim.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SEC MIPI DSIM Bridge controller on i.MX8M Mini and Nano SoCs
+
+maintainers:
+  - Jagan Teki <jagan@amarulasolutions.com>
+
+description: |
+  NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
+  the SOCs NWL MIPI-DSI host controller.
+
+allOf:
+  - $ref: ../dsi-controller.yaml#
+
+properties:
+  compatible:
+    enum:
+      - fsl,imx8mm-sec-dsim
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 0
+
+  assigned-clock-parents: true
+  assigned-clock-rates: true
+  assigned-clocks: true
+
+  clocks:
+    items:
+      - description: DSI bus clock
+      - description: PHY_REF clock
+
+  clock-names:
+    items:
+      - const: bus
+      - const: phy_ref
+
+  phys:
+    maxItems: 1
+    description: phandle to the phy module representing the DPHY
+
+  phy-names:
+    items:
+      - const: dphy
+
+  power-domains:
+    maxItems: 1
+    description: phandle to the associated power domain
+
+  samsung,burst-clock-frequency:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      DSIM high speed burst mode frequency.
+
+  samsung,esc-clock-frequency:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      DSIM escape mode frequency.
+
+  samsung,pll-clock-frequency:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      DSIM oscillator clock frequency.

Why do you need those three properties ? They look like configuration
information to me, not system description. If they are needed, their
description needs to explain how to set them. Looking at the three
descriptions above I have no idea what to select for those frequencies.

DSIM PLLOutput PMS values are computed based on these clock values as
per exynos dsi code is concern. Look like there is other way to
compute PMS in SEC DSIM(at least on i.MX8MM) unlike exynos. Let me
come back with new changes, thanks!

Jagan.

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