Re: [RESEND PATCH v4 11/11] perf/cxl: Clear stale overflow status before using a counter

On Wed,  5 Aug 2026 08:59:11 -0700
Dave Jiang [off-list ref] wrote:

cxl_pmu_event_stop() leaves the counter's bit set in the overflow status
register and only cxl_pmu_irq() ever clears it, so a counter handed from
one event to the next starts with the previous owner's overflow pending.
The perf core stops and starts back to back with interrupts off, so an
interrupt latched over the handover lands on the new event. prev_count is 0
by then, so the read path adds a full period: 2^counter_width phantom
counts.

Clear the bit in cxl_pmu_event_start(), before the config write arms
Interrupt on Overflow. Clear the whole register at probe too, for counters
no event ever owns - the driver never touched it, so firmware or a previous
kernel can leave a bit set there.

Fixes: 5d7107c72796 ("perf: CXL Performance Monitoring Unit driver")
Reported-by: Richard Cheng <redacted>
Closes: https://lore.kernel.org/linux-cxl/anAVpO--i5heVfz9@MWDK4CY14F/ (local)
Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Dave Jiang <dave.jiang@intel.com>

Looks good to me as does the whole series. Thanks for hard work cleaning
up my mess!  Now there is actual hardware out there, I'm kind of expecting
a lot of extensions to the features of this driver as we deliberately
kept it minimal until more was known about what people were actually
building.  I wonder if the limited support did guide folk away from the
sillier things the spec allowed.  Will be fun to see.

Reviewed-by: Jonathan Cameron <redacted>