[PATCH v8 2/6] perf mem: Add support for printing PERF_MEM_LVLNUM_L0
From: Thomas Falcon <hidden>
Date: 2026-09-10 19:44:28
Also in:
lkml
Subsystem:
performance events subsystem, the rest · Maintainers:
Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Namhyung Kim, Linus Torvalds
From: Dapeng Mi <redacted> Add support for printing PERF_MEM_LVLNUM_L0 in perf mem report. The L0 cache is newly added a small piece of cache which is the closest, lowest-latency memory cache tied directly to the execution pipeline. The table "Table 9-4. Data Source Field Encodings for Panther Cove and Coyote Cove Microarchitectures" in the ISE doc chapter "9.2.1 Panther Cove and Coyote Cove Microarchitectures Memory Auxiliary Field Layout"[1] indicates the code "01H" means the "L0 Hit - Minimal latency core cache hit. This request was satisfied by the L0 data cache." [1]: https://www.intel.com/content/www/us/en/content-details/922690/intel-architecture-instruction-set-extensions-programming-reference.html Assisted-by: Sashiko:gemini-3.1-pro-preview Codeveloped-by: Thomas Falcon [off-list ref] Reviewed-by: Dapeng Mi <redacted> Reviewed-by: Ian Rogers <irogers@google.com> Signed-off-by: Dapeng Mi <redacted> Signed-off-by: Thomas Falcon <redacted> --- v8: Updated developer tags v3: Included more information about the L0 cache in the commit message. --- tools/perf/Documentation/perf-record.txt | 2 +- tools/perf/util/bpf-filter.l | 1 + tools/perf/util/mem-events.c | 5 +++++ tools/perf/util/mem-events.h | 1 + 4 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/tools/perf/Documentation/perf-record.txt b/tools/perf/Documentation/perf-record.txt
index 178f483140ed..b54032efe41c 100644
--- a/tools/perf/Documentation/perf-record.txt
+++ b/tools/perf/Documentation/perf-record.txt@@ -212,7 +212,7 @@ OPTIONS The <value> can be one of: <number> (for any term) na, load, store, pfetch, exec (for mem_op) - l1, l2, l3, l4, cxl, io, any_cache, lfb, ram, pmem (for mem_lvl) + l0, l1, l2, l3, l4, cxl, io, any_cache, lfb, ram, pmem (for mem_lvl) na, none, hit, miss, hitm, fwd, peer (for mem_snoop) remote (for mem_remote) na, locked (for mem_locked)
diff --git a/tools/perf/util/bpf-filter.l b/tools/perf/util/bpf-filter.l
index 6aa65ade3385..1be9df6550fc 100644
--- a/tools/perf/util/bpf-filter.l
+++ b/tools/perf/util/bpf-filter.l@@ -131,6 +131,7 @@ store { return constant(PERF_MEM_OP_STORE); } pfetch { return constant(PERF_MEM_OP_PFETCH); } exec { return constant(PERF_MEM_OP_EXEC); } +l0 { return constant(PERF_MEM_LVLNUM_L0); } l1 { return constant(PERF_MEM_LVLNUM_L1); } l2 { return constant(PERF_MEM_LVLNUM_L2); } l3 { return constant(PERF_MEM_LVLNUM_L3); }
diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c
index 4e490f9cd348..4fd48fd20055 100644
--- a/tools/perf/util/mem-events.c
+++ b/tools/perf/util/mem-events.c@@ -391,6 +391,7 @@ static const char * const mem_lvlnum[] = { [PERF_MEM_LVLNUM_L4] = "L4", [PERF_MEM_LVLNUM_L2_MHB] = "L2 MHB", [PERF_MEM_LVLNUM_MSC] = "Memory-side Cache", + [PERF_MEM_LVLNUM_L0] = "L0", [PERF_MEM_LVLNUM_UNC] = "Uncached", [PERF_MEM_LVLNUM_CXL] = "CXL", [PERF_MEM_LVLNUM_IO] = "I/O",
@@ -831,6 +832,8 @@ int mem_stat_index(const enum mem_stat_type mst, const u64 val) } case PERF_MEM_STAT_CACHE: switch (src.mem_lvl_num) { + case PERF_MEM_LVLNUM_L0: + return MEM_STAT_CACHE_L0; case PERF_MEM_LVLNUM_L1: return MEM_STAT_CACHE_L1; case PERF_MEM_LVLNUM_L2:
@@ -915,6 +918,8 @@ const char *mem_stat_name(const enum mem_stat_type mst, const int idx) } case PERF_MEM_STAT_CACHE: switch (idx) { + case MEM_STAT_CACHE_L0: + return "L0"; case MEM_STAT_CACHE_L1: return "L1"; case MEM_STAT_CACHE_L2:
diff --git a/tools/perf/util/mem-events.h b/tools/perf/util/mem-events.h
index 5b98076904b0..daa22748f9fe 100644
--- a/tools/perf/util/mem-events.h
+++ b/tools/perf/util/mem-events.h@@ -109,6 +109,7 @@ enum mem_stat_op { }; enum mem_stat_cache { + MEM_STAT_CACHE_L0, MEM_STAT_CACHE_L1, MEM_STAT_CACHE_L2, MEM_STAT_CACHE_L3,
--
2.43.0