On 5/07/21 10:24 am, Peter Zijlstra wrote:
On Thu, Jul 01, 2021 at 04:17:30PM +0300, Adrian Hunter wrote:
quoted
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index e28892270c58..7a7c3b18acec 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2400,6 +2400,12 @@ static void intel_pmu_disable_event(struct perf_event *event)
intel_pmu_pebs_disable(event);
}
+static void intel_pmu_assign_event(struct perf_event *event, int idx)
+{
+ if (is_pebs_pt(event))
+ perf_report_aux_output_id(event, idx);
+}
+
static void intel_pmu_del_event(struct perf_event *event)
{
if (needs_branch_stack(event))@@ -4596,6 +4602,7 @@ static __initconst const struct x86_pmu intel_pmu = {
.enable_all = intel_pmu_enable_all,
.enable = intel_pmu_enable_event,
.disable = intel_pmu_disable_event,
+ .assign = intel_pmu_assign_event,
.add = intel_pmu_add_event,
.del = intel_pmu_del_event,
.read = intel_pmu_read_event,
How about we only set that method (or clear it again) when
intel_cap.pebs_output_pt_available ?
I've finally got back to this, but now, in the case of hybrids,
there seems to be more than one intel_cap.pebs_output_pt_available.
Any suggestions?
Other than that, this looks good to me.