Re: [PATCH v2] perf/x86/amd: Don't touch the AMD64_EVENTSEL_HOSTONLY bit inside the guest
From: Liam Merwick <hidden>
Date: 2021-08-04 11:29:50
Also in:
lkml
On (08/02/21 15:08), Like Xu wrote:
Date: Mon, 2 Aug 2021 15:08:50 +0800
From: Like Xu <redacted>
To: Peter Zijlstra <peterz@infradead.org>, Joerg Roedel
[off-list ref]
Cc: Ingo Molnar <mingo@redhat.com>, Arnaldo Carvalho de Melo
[off-list ref], Mark Rutland [off-list ref], Alexander Shishkin
[off-list ref], Jiri Olsa [off-list ref],
Namhyung Kim [off-list ref], Thomas Gleixner [off-list ref],
Borislav Petkov [off-list ref], x86@kernel.org, "H . Peter Anvin"
[off-list ref], linux-perf-users@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v2] perf/x86/amd: Don't touch the AMD64_EVENTSEL_HOSTONLY
bit inside the guest
X-Mailer: git-send-email 2.32.0
From: Like Xu <redacted>
If we use "perf record" in an AMD Milan guest, dmesg reports a #GP
warning from an unchecked MSR access error on MSR_F15H_PERF_CTLx:
[] unchecked MSR access error: WRMSR to 0xc0010200 (tried to write
0x0000020000110076) at rIP: 0xffffffff8106ddb4 (native_write_msr+0x4/0x20)
[] Call Trace:
[] amd_pmu_disable_event+0x22/0x90
[] x86_pmu_stop+0x4c/0xa0
[] x86_pmu_del+0x3a/0x140
The AMD64_EVENTSEL_HOSTONLY bit is defined and used on the host,
while the guest perf driver should avoid such use.
Fixes: 1018faa6cf23 ("perf/x86/kvm: Fix Host-Only/Guest-Only counting with SVM disabled")
Signed-off-by: Like Xu <redacted>
Tested-by: Kim Phillips <redacted>Reviewed-by: Liam Merwick <redacted> Tested-by: Liam Merwick <redacted> [ Patch applied to a 5.4 branch ] Should it also include Cc: stable@vger.kernel.org Regards, Liam
quoted hunk ↗ jump to hunk
--- v2: Add Fixes tag and Tested-by from Kim. v1: https://lore.kernel.org/lkml/20210720112605.63286-1-likexu@tencent.com/ (local) arch/x86/events/perf_event.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index d6003e08b055..1c3ae954a230 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h@@ -1116,8 +1116,9 @@ void x86_pmu_stop(struct perf_event *event, int flags); static inline void x86_pmu_disable_event(struct perf_event *event) { struct hw_perf_event *hwc = &event->hw; + u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); - wrmsrl(hwc->config_base, hwc->config); + wrmsrl(hwc->config_base, hwc->config & ~disable_mask); if (is_counter_pair(hwc)) wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0);-- 2.32.0