[PATCH 3/4] perf/x86/intel/uncore: Constify freerunning_counters
From: Rikard Falkeborn <hidden>
Date: 2021-06-05 15:58:07
Also in:
lkml
Subsystem:
performance events subsystem, the rest, x86 architecture (32-bit and 64-bit) · Maintainers:
Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Namhyung Kim, Linus Torvalds, Thomas Gleixner, Borislav Petkov, Dave Hansen
These are never modified, so make them const to allow the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn <redacted> --- arch/x86/events/intel/uncore.h | 4 ++-- arch/x86/events/intel/uncore_snb.c | 6 +++--- arch/x86/events/intel/uncore_snbep.c | 14 +++++++------- 3 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h
index 83b25a7b8c27..6a7f0104bb38 100644
--- a/arch/x86/events/intel/uncore.h
+++ b/arch/x86/events/intel/uncore.h@@ -79,7 +79,7 @@ struct intel_uncore_type { struct intel_uncore_pmu *pmus; const struct intel_uncore_ops *ops; struct uncore_event_desc *event_descs; - struct freerunning_counters *freerunning; + const struct freerunning_counters *freerunning; const struct attribute_group *attr_groups[4]; const struct attribute_group **attr_update; struct pmu *pmu; /* for custom pmu ops */
@@ -175,7 +175,7 @@ struct freerunning_counters { unsigned int box_offset; unsigned int num_counters; unsigned int bits; - unsigned *box_offsets; + const unsigned *box_offsets; }; struct intel_uncore_topology {
diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/uncore_snb.c
index 3eff6f1a5b99..475e48b7a686 100644
--- a/arch/x86/events/intel/uncore_snb.c
+++ b/arch/x86/events/intel/uncore_snb.c@@ -603,7 +603,7 @@ enum perf_snb_uncore_imc_freerunning_types { SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX, }; -static struct freerunning_counters snb_uncore_imc_freerunning[] = { +static const struct freerunning_counters snb_uncore_imc_freerunning[] = { [SNB_PCI_UNCORE_IMC_DATA_READS] = { SNB_UNCORE_PCI_IMC_DATA_READS_BASE, 0x0, 0x0, 1, 32 }, [SNB_PCI_UNCORE_IMC_DATA_WRITES] = { SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE,
@@ -1344,13 +1344,13 @@ enum perf_tgl_uncore_imc_freerunning_types { TGL_MMIO_UNCORE_IMC_FREERUNNING_TYPE_MAX }; -static struct freerunning_counters tgl_l_uncore_imc_freerunning[] = { +static const struct freerunning_counters tgl_l_uncore_imc_freerunning[] = { [TGL_MMIO_UNCORE_IMC_DATA_TOTAL] = { 0x5040, 0x0, 0x0, 1, 64 }, [TGL_MMIO_UNCORE_IMC_DATA_READ] = { 0x5058, 0x0, 0x0, 1, 64 }, [TGL_MMIO_UNCORE_IMC_DATA_WRITE] = { 0x50A0, 0x0, 0x0, 1, 64 }, }; -static struct freerunning_counters tgl_uncore_imc_freerunning[] = { +static const struct freerunning_counters tgl_uncore_imc_freerunning[] = { [TGL_MMIO_UNCORE_IMC_DATA_TOTAL] = { 0xd840, 0x0, 0x0, 1, 64 }, [TGL_MMIO_UNCORE_IMC_DATA_READ] = { 0xd858, 0x0, 0x0, 1, 64 }, [TGL_MMIO_UNCORE_IMC_DATA_WRITE] = { 0xd8A0, 0x0, 0x0, 1, 64 },
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index b5b22fe473d8..507bb83e1463 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c@@ -3885,7 +3885,7 @@ enum perf_uncore_iio_freerunning_type_id { }; -static struct freerunning_counters skx_iio_freerunning[] = { +static const struct freerunning_counters skx_iio_freerunning[] = { [SKX_IIO_MSR_IOCLK] = { 0xa45, 0x1, 0x20, 1, 36 }, [SKX_IIO_MSR_BW] = { 0xb00, 0x1, 0x10, 8, 36 }, [SKX_IIO_MSR_UTIL] = { 0xb08, 0x1, 0x10, 8, 36 },
@@ -4588,7 +4588,7 @@ enum perf_uncore_snr_iio_freerunning_type_id { SNR_IIO_FREERUNNING_TYPE_MAX, }; -static struct freerunning_counters snr_iio_freerunning[] = { +static const struct freerunning_counters snr_iio_freerunning[] = { [SNR_IIO_MSR_IOCLK] = { 0x1eac, 0x1, 0x10, 1, 48 }, [SNR_IIO_MSR_BW_IN] = { 0x1f00, 0x1, 0x10, 8, 48 }, };
@@ -4931,7 +4931,7 @@ enum perf_uncore_snr_imc_freerunning_type_id { SNR_IMC_FREERUNNING_TYPE_MAX, }; -static struct freerunning_counters snr_imc_freerunning[] = { +static const struct freerunning_counters snr_imc_freerunning[] = { [SNR_IMC_DCLK] = { 0x22b0, 0x0, 0, 1, 48 }, [SNR_IMC_DDR] = { 0x2290, 0x8, 0, 2, 48 }, };
@@ -5153,15 +5153,15 @@ enum perf_uncore_icx_iio_freerunning_type_id { ICX_IIO_FREERUNNING_TYPE_MAX, }; -static unsigned icx_iio_clk_freerunning_box_offsets[] = { +static const unsigned icx_iio_clk_freerunning_box_offsets[] = { 0x0, 0x20, 0x40, 0x90, 0xb0, 0xd0, }; -static unsigned icx_iio_bw_freerunning_box_offsets[] = { +static const unsigned icx_iio_bw_freerunning_box_offsets[] = { 0x0, 0x10, 0x20, 0x90, 0xa0, 0xb0, }; -static struct freerunning_counters icx_iio_freerunning[] = { +static const struct freerunning_counters icx_iio_freerunning[] = { [ICX_IIO_MSR_IOCLK] = { 0xa55, 0x1, 0x20, 1, 48, icx_iio_clk_freerunning_box_offsets }, [ICX_IIO_MSR_BW_IN] = { 0xaa0, 0x1, 0x10, 8, 48, icx_iio_bw_freerunning_box_offsets }, };
@@ -5443,7 +5443,7 @@ enum perf_uncore_icx_imc_freerunning_type_id { ICX_IMC_FREERUNNING_TYPE_MAX, }; -static struct freerunning_counters icx_imc_freerunning[] = { +static const struct freerunning_counters icx_imc_freerunning[] = { [ICX_IMC_DCLK] = { 0x22b0, 0x0, 0, 1, 48 }, [ICX_IMC_DDR] = { 0x2290, 0x8, 0, 2, 48 }, [ICX_IMC_DDRT] = { 0x22a0, 0x8, 0, 2, 48 },
--
2.31.1