On Thu, Dec 09 2021 at 16:58, Jason Gunthorpe wrote:
On Thu, Dec 09, 2021 at 09:32:42PM +0100, Thomas Gleixner wrote:
quoted
That was my thought to avoid having different mechanisms.
The address/data pair is computed in two places:
1) Activation of an interrupt
2) Affinity setting on an interrupt
Both configure the IRTE when interrupt remapping is in place.
In both cases a vector is allocated in the vector domain and based on
the resulting target APIC / vector number pair the IRTE is
(re)configured.
So putting the hypercall into the vIRTE update is the obvious
place. Both activation and affinity setting can fail and propagate an
error code down to the originating caller.
Hmm?
Okay, I think I get it. Would be nice to have someone from intel
familiar with the vIOMMU protocols and qemu code remark what the
hypervisor side can look like.
There is a bit more work here, we'd have to change VFIO to somehow
entirely disconnect the kernel IRQ logic from the MSI table and
directly pass control of it to the guest after the hypervisor IOMMU IR
secures it. ie directly mmap the msi-x table into the guest
That makes everything consistent and a clear cut on all levels, right?
Thanks,
tglx