On Wed, 26 May 2021 at 15:55, Christian König
[off-list ref] wrote:

Hi Ard,

Am 25.05.21 um 19:18 schrieb Ard Biesheuvel:

quoted

[SNIP]

quoted

quoted

I seriously doubt that this is what is going on here.

lspci -x will give you the bare BAR values - I suspect that those are
probably fine.

lspci -x
00:00.0 PCI bridge: Fuzhou Rockchip Electronics Co., Ltd Device 3566 (rev 01)
00: 87 1d 66 35 07 05 10 40 01 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 01 ff 00 10 10 00 20
20: 00 10 00 10 01 00 f1 0f 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 5f 01 02 00

01:00.0 VGA compatible controller: Advanced Micro Devices, Inc.
[AMD/ATI] Turks PRO [Radeon HD 7570]
00: 02 10 5d 67 07 00 10 20 00 00 00 03 00 00 80 00
10: 0c 00 00 00 00 00 00 00

This is a 64-bit prefetchable BAR programmed with bus address 0x0

quoted

04 00 00 10 00 00 00 00

This is a 64-bit non-prefetchable BAR programmed with bus address 0x1000_0000

(https://en.wikipedia.org/wiki/PCI_configuration_space describes the
meaning of the low order BAR bits)

Sorry for jumping into the middle of the discussion and to be honest I
haven't fully read it.

This looks a bit odd since on AMD VGA hardware the non-prefetchable BAR
is usually only 32bit, not 64bit.

But this hardware generation is rather old and I'm not sure what the BAR
assignment for that generation was. I would need to dig up the register
description in our archives as well.

I have another museum piece in my AMD Seattle:

02:00.0 VGA compatible controller: Advanced Micro Devices, Inc.
[AMD/ATI] Oland XT [Radeon HD 8670 / R7 250/350] (rev 81) (prog-if 00
[VGA controller])
  Subsystem: Dell Oland XT [Radeon HD 8670 / R7 250/350]
  Flags: bus master, fast devsel, latency 0, IRQ 255
  Memory at 100000000 (64-bit, prefetchable) [size=4G]
  Memory at 40000000 (64-bit, non-prefetchable) [size=256K]
  I/O ports at 1000 [disabled] [size=256]
  Expansion ROM at 40060000 [disabled] [size=128K]
  Capabilities: <access denied>
  Kernel modules: radeon, amdgpu

So AMD/ATI ASICs definitely exist that expose a 64-bit pref and a
64-bit non-pref BAR.

-- 
Ard.