Re: [PATCH v4 5/8] cxl/acpi: Introduce ACPI0017 driver and cxl_root

On Fri, May 14, 2021 at 2:19 AM Jonathan Cameron
[off-list ref] wrote:

On Thu, 13 May 2021 22:22:10 -0700
Dan Williams [off-list ref] wrote:

quoted

While CXL builds upon the PCI software model for dynamic enumeration and
control, a static platform component is required to bootstrap the CXL
memory layout. In addition to identifying the host bridges ACPI is
responsible for enumerating the CXL memory space that can be addressed
by decoders. This is similar to the requirement for ACPI to publish
resources reported by _CRS for PCI host bridges.

Introduce the cxl_root object as an abstract "port" into the CXL.mem
address space described by HDM decoders identified by the ACPI
CEDT.CHBS.

For now just establish the initial boilerplate and sysfs attributes, to
be followed by enumeration of the ports within the host bridge.

Note the allocation of CXL core device objects is split into separate
alloc and add steps in order to separate the alloc error path (kfree())
from the device add error path (put_device()).

Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dan Williams <redacted>

A few really minor editorial things in the docs that need tidying up.

Sure, I'm going to see if b4 can follow a v5 reply to just this one
patch, or otherwise hack it to support that flow so I don't need to
resend the full series.

With that done
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

I'll make the bold assumption that this is going to get applied
before the DOE series and base that on top of this one.

Yes, the plan is to make the 'next' branch of:

git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git

...the stable non-rebasing development branch for contributions. bf gntcbttttt

Thanks,

Jonathan

quoted

---
 Documentation/ABI/testing/sysfs-bus-cxl |   78 +++++++
 drivers/cxl/Kconfig                     |   14 +
 drivers/cxl/Makefile                    |    2
 drivers/cxl/acpi.c                      |   39 +++
 drivers/cxl/core.c                      |  360 +++++++++++++++++++++++++++++++
 drivers/cxl/cxl.h                       |   65 ++++++
 6 files changed, 558 insertions(+)
 create mode 100644 drivers/cxl/acpi.c

diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl
index 2fe7490ad6a8..d21469e2bf8b 100644
--- a/Documentation/ABI/testing/sysfs-bus-cxl
+++ b/Documentation/ABI/testing/sysfs-bus-cxl

@@ -24,3 +24,81 @@ Description:
              (RO) "Persistent Only Capacity" as bytes. Represents the
              identically named field in the Identify Memory Device Output
              Payload in the CXL-2.0 specification.
+
+What:           /sys/bus/cxl/devices/address_spaceX/start
+Date:           May, 2021
+KernelVersion:  v5.14
+Contact:        linux-cxl@vger.kernel.org
+Description:

I'm not that fussy about this, but others may comment on wrapping lines around 70 chars
whereas can at least go to 80 for docs.

Sure I can reflow.

quoted

+             (RO) System-physical base address for an address range
+             that supports CXL.mem targets. A CXL address space can
+             be optionally populated with endpoints that decode that
+             range, similar to how devices behind a PCI bridge can
+             decode a portion of the bridge's secondary bus address
+             space.
+
+What:           /sys/bus/cxl/devices/address_spaceX/end
+Date:           May, 2021
+KernelVersion:  v5.14
+Contact:        linux-cxl@vger.kernel.org
+Description:
+             (RO) System-physical end address for an address range
+             that supports CXL.mem targets. A CXL address space can
+             be optionally populated with endpoints that decode that
+             range, similar to how devices behind a PCI bridge can
+             decode a portion of the bridge's secondary bus address
+             space.
+
+What:                /sys/bus/cxl/devices/address_spaceX/supports_ram

Inconsistent tabs vs spaces.

ok.