Re: [PATCH v2 4/6] dt-bindings: PCI: Add SiFive FU740 PCIe host controller
From: Greentime Hu <greentime.hu@sifive.com>
Date: 2021-03-29 03:40:55
Also in:
linux-clk, linux-devicetree, linux-riscv, lkml
Rob Herring [off-list ref] 於 2021年3月24日 週三 上午4:35寫道：
On Thu, Mar 18, 2021 at 02:08:11PM +0800, Greentime Hu wrote:quoted
Add PCIe host controller DT bindings of SiFive FU740. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> --- .../bindings/pci/sifive,fu740-pcie.yaml | 119 ++++++++++++++++++ 1 file changed, 119 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
[...]
quoted
+examples: + - | + pcie@e00000000 { + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + compatible = "sifive,fu740-pcie"; + reg = <0xe 0x00000000 0x1 0x0Humm, 4GB for DBI space? The DWC controller doesn't have that much space, and the kernel will map *all* of that. That's not an insignificant amount of memory just for page tables.
Thank you for review and point this out. :) I check the spec description for DBI in DWC_pcie_ctl_dm_databook.pdf section 3.15 3.16 and table 3-17. I think CX_SRIOV_ENABLE and CX_ARI_ENABLE will be set to 0 because these 2 are endpoint mode features. Single Root I/O Virtualization (SR-IOV) This section describes the SR-IOV features implemented in EP mode. The parameter for enabling SR-IOV is CX_SRIOV_ENABLE Alternative Routing-ID Interpretation (ARI) ARI allows an endpoint to support more than eight physical functions (PFs). ARI is enabled by the CX_ARI_ENABLE parameter. So based on Table 3-17, we will need to map 2GB(bit30) instead of 4GB(bit31).