Hi Joao,

On Monday 16 January 2017 03:57 PM, Joao Pinto wrote:

=

Hi,
=

=C0s 5:21 AM de 1/16/2017, Kishon Vijay Abraham I escreveu:

quoted

Hi Joao,

On Friday 13 January 2017 10:19 PM, Joao Pinto wrote:

quoted

=C0s 10:26 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:

quoted

Split pcie-designware.c into pcie-designware-host.c that contains
the host specific parts of the driver and pcie-designware.c that
contains the parts used by both host driver and endpoint driver.

Signed-off-by: Kishon Vijay Abraham I <redacted>
---
 drivers/pci/dwc/Makefile               |    2 +-
 drivers/pci/dwc/pcie-designware-host.c |  619 +++++++++++++++++++++++=

+++++++++

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 drivers/pci/dwc/pcie-designware.c      |  613 +----------------------=

--------

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 drivers/pci/dwc/pcie-designware.h      |    8 +
 4 files changed, 634 insertions(+), 608 deletions(-)
 create mode 100644 drivers/pci/dwc/pcie-designware-host.c

diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
index 7d27c14..3b57e55 100644
--- a/drivers/pci/dwc/Makefile
+++ b/drivers/pci/dwc/Makefile

@@ -1,4 +1,4 @@

(snip...)

quoted

-static void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
-				      int type, u64 cpu_addr, u64 pci_addr,
-				      u32 size)
+void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int ty=

pe,

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+			       u64 cpu_addr, u64 pci_addr, u32 size)
 {
 	u32 retries, val;
 =

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@@ -186,220 +151,6 @@ static void dw_pcie_prog_outbound_atu(struct dw_=

pcie *pci, int index,

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 	dev_err(pci->dev, "iATU is not being enabled\n");
 }

Kishon, iATU only makes sense in The Root Complex (host), so it should =

be inside

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the pcie-designware-host.

That is not true. Outbound ATU should be programmed to access host side =

buffers

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and inbound ATU should be programmed for the host to access EP mem space.

=

Sorry, I was not clear enough. What I was trying to suggest is, since the=

 ATU

programming is done by the host, wouldn't be better to include it in the
pcie-designware-host? It is just an architectural detail.

ATU programming is required in EP mode. See "[PATCH 24/37] PCI: dwc:
designware: Add EP mode support" in this patch series.

Anything that's required by both EP mode and RC mode, I've placed in
pcie-designware.c

Thanks
Kishon

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