RE: [PATCH 4/5] ARM: scu: Move register defines to header file

-----Original Message-----
From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk]
Sent: Tuesday, January 25, 2011 7:11 PM
To: Santosh Shilimkar
Cc: linux-arm-kernel@lists.infradead.org; catalin.marinas@arm.com;
ccross@android.com; linus.ml.walleij@gmail.com; linux-
omap@vger.kernel.org
Subject: Re: [PATCH 4/5] ARM: scu: Move register defines to header
file

On Tue, Jan 25, 2011 at 06:06:27PM +0530, Santosh Shilimkar wrote:

quoted

Ok. I missed some information my last email.
The SCU power status programming is used to take CPU in/out
of coherency as an alternative to SMP bit. We don't
have an access to SMP bit on OMAP4. ARM has already
confirmed SCU programming is same as SMP bit enable/disable.

I don't know how safe is to use spin lock when one CPU is
goes out of coherency after programming the power state. The
spin lock release may not even be visible to other CPU.
The programming happens from IDLE or suspend where the

BTW, presumably we should be flushing the caches/tlbs before setting
the CPU power register to a non-normal setting?

Yes but only till inner shareability domain. i.e L1
L2 will be flushed after this. This is one more issue
where the current L2 cache current APIs(use locks) becomes
not so suitable.

I'll wait until there's more information available (such as an
example
implementation.)