On Sat, Sep 25, 2021, at 22:38, Keith Busch wrote:

On Sat, Sep 25, 2021 at 10:08:53PM +0200, Sven Peter wrote:

quoted

I actually ran into a similar issue while adding support for the NVMe
controller found on the M1 and assumed it was only present there.

Some background why this happens: ANS2 is a co-processor that emulates
an NVMe MMIO interface and uses the tag as an index to an internal data
structure. 

Thanks for confirming the behavior. The patch should restore the
command_id values to when everything was working. I'll just need to
update the quirk description to better align with the actual limitation
if the patch is successful. 

quoted

On the M1 we can directly talk to ANS2 and while we can submit
commands with a higher index it'll just ignore the upper bits and only
return the lowest eight IIRC in the completion queue.
I guess whatever software is running on the T2 actually has an assert to
ensure that the tag is within the limits before forwarding the command
to ANS2.

Is the PCI Device ID for the M1 the same as reported for the T2? Either
0x2005 or 0x2003 should make this quirk apply.

Oh, it's worse. It's no longer a PCIe device there but a platform device
directly attached to the SoC's bus. It'll need almost all T2 quirks and then
some additional changes to the way command submission works and support to
program a tightly coupled IOMMU which Apple calls NVMMU (which probably is another
reason for this limit: they use the command id to find the corresponding entry in
the IOMMU that allows access to memory listed in the PRPs).
I'll just use the quirk in my platform driver and submit it once I get it into a
shape that can actually be reviewed.



Sven


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