On 8/10/21 9:23 PM, Baoquan He wrote:

On 08/10/21 at 03:52pm, Tom Lendacky wrote:

quoted

On 8/5/21 1:54 AM, Baoquan He wrote:

quoted

On 06/24/21 at 11:47am, Robin Murphy wrote:

quoted

On 2021-06-24 10:29, Baoquan He wrote:

quoted

On 06/24/21 at 08:40am, Christoph Hellwig wrote:

...

Looking at the those related commits, the below one from David tells 
that atomic dma pool is used when device require non-blocking and
unencrypted buffer. When I checked the system I borrowed, it's AMD EYPC
and SME is enabled. And it has many pci devices, as you can see, its 'ls
pci' outputs 113 lines. But disabling the three atomic pools didn't
trigger any error on that AMD system. Does it mean only specific devices
need this atomic pool in SME/SEV enabling case? Should we add more
details in document or code comment to make clear this? 

It very well could be just the devices being used. Under SME (bare metal),
if a device supports 64-bit DMA, then bounce buffers aren't used and the
DMA can be performed directly to encrypted memory, so there is no need to
issue a set_memory_decrypted() call, so I would assume it likely isn't
using the pool.

Under SEV, however, all DMA has to go through guest un-encrypted memory.
If you pass through a device that does dma_alloc_coherent() calls with
GFP_ATOMIC, then the pool will be needed.

Thanks,
Tom