On Fri, Jun 25, 2021 at 09:38:18PM +1000, Michael Ellerman wrote:

Dave Hansen [off-list ref] writes:

quoted

I'd like to have a session about new hardware features that may will
have an impact on core memory management.  This session would have two
goals: one to ensure that the OS-agnostic MM crowd understands what the
architectures are going to be throwing their way.  Second, that the
different arch-specific folks can look for commonalities which could
enable shared infrastructure.

I'm interested in this subject.

quoted

There should be enough x86 folks around, but I'd love to hear from the
ARM and powerpc people as well.

Cc += Aneesh and Nick

I can't think of anything publicly announced for Power that will have a
big impact on core mm, but Nick & Aneesh might have ideas.

cheers

quoted

Here are a few mostly Intel-specific things I'd like to discuss.
However, all of these either have analogs on other architectures or are
implemented by other x86 vendors.

 * Shadow Stacks - requires new Copy-on-Read memory type.  Creates
   application mappings which are effectively PROT_NONE, but which are
   implicitly accessible by the hardware.
 * Linear Address Masking (LAM) - Similar to ARM's Top Byte Ignore
   (TBI).  Repurpose some virtual address bits to store metadata.  Intel
   implementation can sacrifice user address space.  Offloads some of
   the work the compiler does in ASAN implementations.
 * Supervisor Protection Keys - Extends Memory Protection Keys (pkeys)
   to kernel mappings.

I'd be more than happy to share what I've tried to do to make this support
generic.

Ira

quoted

 * TDX - VMs that don't trust the hypervisor.  Requires unmapping guest
   memory from userspace and possibly the host kernel.