On Wed, 2016-02-03 at 13:41 +0200, Oded Gabbay wrote:

It seems you have most of your bases covered. I'll stop harassing you now :)
But in seriousness, its interesting to see the different approaches
taken to handling pretty much the same type of H/W (IOMMU).

Well, the point is that we need to settle on a model we can *all* use.

It's all very well having vendor-specific intel_svm_bind_mm() and
amd_iommu_bind_pasid() functions with subtly different semantics, while
the only devices we support for Intel are integrated graphics and our
PCIe root ports don't even support discrete devices with PASID
capabilities — and while the only device using the AMD version is the
AMD GPU.

But we *are* starting to see additional devices with PASID
capabilities, and it won't be long before we really do have to support
third-party discrete devices.

So we do need a coherent API for SVM, as an extension of the DMA API.
And that means we have to settle on the semantics we want for it :)

With the commit I showed earlier, I've moved the Intel model somewhat
closer to the AMD model — no longer holding mm_users on the MM in
question. I think we can come up with something acceptable. 

There are Power and ARM incarnations of SVM also in the works, I
believe.

-- 
David Woodhouse                            Open Source Technology Centre
David.Woodhouse@intel.com                              Intel Corporation