On Sat, Nov 17, 2012 at 1:53 PM, Shentino [off-list ref] wrote:

I'm actually curious if the architecture docs/software developer
manuals for IA-32 mandate any TLB invalidations on a #PF

Is there any official vendor documentation on the subject?

Yes. Quoting a prior email:

Actually, it is architected on x86. This was first described in the
intel appnote 317080 "TLBs, Paging-Structure Caches, and Their
Invalidation", last paragraph of section 5.1. Nowadays, the same
contents are buried somewhere in Volume 3 of the architecture manual
(in my copy: 4.10.4.1 Operations that Invalidate TLBs and
Paging-Structure Caches)

And perhaps equally valid, should we trust it if it exists?

I know that Intel has been very careful in documenting the architected
TLB behaviors and did it with the understanding that people should be
able to depend on what's being written up there.

-- 
Michel "Walken" Lespinasse
A program is never fully debugged until the last user dies.

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