[PATCH] MIPS: sead3: Fix incorrect values for soft reset.

The soft reset register address and reset value to be written to
the register are incorrect for the SEAD-3 platform. This patch
fixes them such that the SEAD-3 can actually perform a soft reset
instead of causing a NMI exception.

Signed-off-by: Steven J. Hill <redacted>
---
 arch/mips/include/asm/mips-boards/generic.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h
index bd9746f..61db690 100644
--- a/arch/mips/include/asm/mips-boards/generic.h
+++ b/arch/mips/include/asm/mips-boards/generic.h

@@ -26,8 +26,8 @@
 /*
  * Reset register.
  */
-#define SOFTRES_REG	  0x1f000500
-#define GORESET		  0x42
+#define SOFTRES_REG	  0x1f000050
+#define GORESET		  0x4d
 
 /*
  * Revision register.

-- 
1.7.2.5

On Wed, Jun 12, 2013 at 05:20:56PM -0500, Steven J. Hill wrote:

I think this is going to break Malta.  We used to have:

    #define SOFTRES_REG       0x1e800050
    #define GORESET           0x4d

for SEAD and

    #define SOFTRES_REG       0x1f000500
    #define GORESET           0x42

for Atlas (no longer supported) and Malta.

  Ralf

On 06/13/2013 09:18 AM, Ralf Baechle wrote:

On Wed, Jun 12, 2013 at 05:20:56PM -0500, Steven J. Hill wrote:

I think this is going to break Malta.  We used to have:

     #define SOFTRES_REG       0x1e800050
     #define GORESET           0x4d

for SEAD

Yes, it does break Malta. The #define values are defined in two places and I missed one of them. I have submitted a patchset to these cleaned up. Both platforms can now perform soft resets. Also, the 0x1e800050 is not correct. I check all the way back in our 2.6.32.15 tree and that value does not show up anywhere. The value in the patchset for SEAD-3 is the correct one.

-Steve