On Wed, Feb 20, 2002 at 03:46:32PM +0100, Maciej W. Rozycki wrote:
quoted
The context register is actually intended to be used for indexing a flat
4mb array of pagetables on a 32-bit processor. It's a bit ill-defined
on R4000-class processors as it assumes a size of 8 bytes per pte, so
cannot be used in the Linux/MIPS kernel without shifting bits around.
Ill??? I think someone was just longsighted enough not to limit PTEs to
38-bit physical addresses. A shift costs a single cycle if we want to
save memory.
The idea of the register was to directly generate the address of a PTE.
An extra instruction in TLB exception handlers isn't only visible in
performance, it also means introducing constraints on the address itself -
an arithmetic shift by one bit for 4 byte PTEs will result in the two
high bits of the address being identical, an arithmetic shift will make
the high bit a null etc. Just on 32-bit kernels on 64-bit hw you're
lucky, you have a bit 32 in c0_context which will be shifted into bit 31.
Messy?
Ralf
On Wed, 20 Feb 2002, Ralf Baechle wrote:
quoted
Ill??? I think someone was just longsighted enough not to limit PTEs to
38-bit physical addresses. A shift costs a single cycle if we want to
save memory.
The idea of the register was to directly generate the address of a PTE.
And it does -- doesn't it? It simply cannot fit all needs at once. What
about pages larger than 4kB, for example?
An extra instruction in TLB exception handlers isn't only visible in
performance, it also means introducing constraints on the address itself -
The performance is an issue, of course -- you get about 10% hit in the
exception handler. You need to decide (possibly at the run time) what's
more important: the gain from a faster TLB refill or the gain from a
compression of page tables.
an arithmetic shift by one bit for 4 byte PTEs will result in the two
high bits of the address being identical, an arithmetic shift will make
the high bit a null etc. Just on 32-bit kernels on 64-bit hw you're
lucky, you have a bit 32 in c0_context which will be shifted into bit 31.
Since the address is virtual -- what's the deal?
Messy?
Hardly.
--
+ Maciej W. Rozycki, Technical University of Gdansk, Poland +
+--------------------------------------------------------------+
+ e-mail: macro@ds2.pg.gda.pl, PGP key available +