Re: [PATCH v5 5/5] arm64: dts: mediatek: add clock support for mt7986b
From: Miles Chen <hidden>
Date: 2021-10-19 04:41:12
Also in:
linux-arm-kernel, linux-clk, linux-devicetree, lkml
Hi Sam,
@@ -99,6 +101,18 @@ gic: interrupt-controller@c000000 { interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
+ infracfg: infracfg@10001000 {
+ compatible = "mediatek,mt7986-infracfg",
"syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ topckgen: topckgen@1001b000 {
+ compatible = "mediatek,mt7986-topckgen",
"syscon";
+ reg = <0 0x1001B000 0 0x1000>;please use lowercase hex values (e.g, 0x1001b000)
quoted hunk ↗ jump to hunk
+ #clock-cells = <1>; + }; + watchdog: watchdog@1001c000 { compatible = "mediatek,mt7986-wdt", "mediatek,mt6589-wdt";@@ -108,11 +122,31 @@ watchdog: watchdog@1001c000 { status = "disabled"; }; + apmixedsys: apmixedsys@1001e000 { + compatible = "mediatek,mt7986-apmixedsys"; + reg = <0 0x1001E000 0 0x1000>; + #clock-cells = <1>; + };
Ditto
quoted hunk ↗ jump to hunk
+ + sgmiisys0: syscon@10060000 { + compatible = "mediatek,mt7986-sgmiisys_0", + "syscon"; + reg = <0 0x10060000 0 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@10070000 { + compatible = "mediatek,mt7986-sgmiisys_1", + "syscon"; + reg = <0 0x10070000 0 0x1000>; + #clock-cells = <1>; + }; + trng: trng@1020f000 { compatible = "mediatek,mt7986-rng", "mediatek,mt7623-rng"; reg = <0 0x1020f000 0 0x100>; - clocks = <&system_clk>; + clocks = <&infracfg CLK_INFRA_TRNG_CK>; clock-names = "rng"; status = "disabled"; };@@ -122,7 +156,13 @@ uart0: serial@11002000 { "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&system_clk>; + clocks = <&infracfg CLK_INFRA_UART0_SEL>, + <&infracfg CLK_INFRA_UART0_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfgCLK_INFRA_UART0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, + <&topckgen CLK_TOP_UART_SEL>; status = "disabled"; };@@ -131,7 +171,11 @@ uart1: serial@11003000 { "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x400>; interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&system_clk>; + clocks = <&infracfg CLK_INFRA_UART1_SEL>, + <&infracfg CLK_INFRA_UART1_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&infracfgCLK_INFRA_UART1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; status = "disabled"; };@@ -140,10 +184,24 @@ uart2: serial@11004000 { "mediatek,mt6577-uart"; reg = <0 0x11004000 0 0x400>; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&system_clk>; + clocks = <&infracfg CLK_INFRA_UART2_SEL>, + <&infracfg CLK_INFRA_UART2_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&infracfgCLK_INFRA_UART2_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; status = "disabled"; }; + ethsys: syscon@15000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt7986-ethsys", + "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; };
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