Re: [PATCH v5 04/16] dt-bindings: reset: mt8195: add vdosys1 reset control bit
From: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Date: 2021-09-07 16:07:15
Also in:
dri-devel, linux-arm-kernel, linux-devicetree, lkml
Hi, Nancy: Nancy.Lin [off-list ref] 於 2021年9月6日 週一 下午3:15寫道：
quoted hunk ↗ jump to hunk
Add vdosys1 reset control bit for MT8195 platform. Signed-off-by: Nancy.Lin <redacted> --- include/dt-bindings/reset/mt8195-resets.h | 12 ++++++++++++ 1 file changed, 12 insertions(+)diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h index a26bccc8b957..eaaa882c09bd 100644 --- a/include/dt-bindings/reset/mt8195-resets.h +++ b/include/dt-bindings/reset/mt8195-resets.h@@ -26,4 +26,16 @@ #define MT8195_TOPRGU_SW_RST_NUM 16 +/* VDOSYS1 */ +#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25 +#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26 +#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27 +#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28 +#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55
Maybe you should align the indent style with TOPRGU. Regards, Chun-Kuang.
+ #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */ -- 2.18.0
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