Hi Chun-Kuang,

Thanks for the review.

On Thu, 2021-08-19 at 23:12 +0800, Chun-Kuang Hu wrote:

Hi, Jason:

jason-jh.lin [off-list ref] 於 2021年8月19日 週四 上午10:23寫道：

quoted

Add mtk-mutex support for mt8195 vdosys0.

Signed-off-by: jason-jh.lin <redacted>
---
 drivers/soc/mediatek/mtk-mutex.c | 98
+++++++++++++++++++++++++++++++-
 1 file changed, 95 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mutex.c

b/drivers/soc/mediatek/mtk-mutex.c
index 2e4bcc300576..c177156ee2fa 100644

--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c

@@ -17,6 +17,9 @@
 #define MT8183_MUTEX0_MOD0                     0x30
 #define MT8183_MUTEX0_SOF0                     0x2c

+#define MT8195_DISP_MUTEX0_MOD0                        0x30
+#define MT8195_DISP_MUTEX0_SOF                 0x2c
+
 #define DISP_REG_MUTEX_EN(n)                   (0x20 + 0x20 * (n))
 #define DISP_REG_MUTEX(n)                      (0x24 + 0x20 * (n))
 #define DISP_REG_MUTEX_RST(n)                  (0x28 + 0x20 * (n))

@@ -67,6 +70,36 @@
 #define MT8173_MUTEX_MOD_DISP_PWM1             24
 #define MT8173_MUTEX_MOD_DISP_OD               25

+#define MT8195_MUTEX_MOD_DISP_OVL0             0
+#define MT8195_MUTEX_MOD_DISP_WDMA0            1
+#define MT8195_MUTEX_MOD_DISP_RDMA0            2
+#define MT8195_MUTEX_MOD_DISP_COLOR0           3
+#define MT8195_MUTEX_MOD_DISP_CCORR0           4
+#define MT8195_MUTEX_MOD_DISP_AAL0             5
+#define MT8195_MUTEX_MOD_DISP_GAMMA0           6
+#define MT8195_MUTEX_MOD_DISP_DITHER0          7
+#define MT8195_MUTEX_MOD_DISP_DSI0             8
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0  9
+#define MT8195_MUTEX_MOD_DISP_OVL1             10
+#define MT8195_MUTEX_MOD_DISP_WDMA1            11
+#define MT8195_MUTEX_MOD_DISP_RDMA1            12
+#define MT8195_MUTEX_MOD_DISP_COLOR1           13
+#define MT8195_MUTEX_MOD_DISP_CCORR1           14
+#define MT8195_MUTEX_MOD_DISP_AAL1             15
+#define MT8195_MUTEX_MOD_DISP_GAMMA1           16
+#define MT8195_MUTEX_MOD_DISP_DITHER1          17
+#define MT8195_MUTEX_MOD_DISP_DSI1             18
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1  19
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE                20
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0         21
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0   22
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1   23
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2   24
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3   25
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4   26
+#define MT8195_MUTEX_MOD_DISP_PWM0             27
+#define MT8195_MUTEX_MOD_DISP_PWM1             28
+
 #define MT2712_MUTEX_MOD_DISP_PWM2             10
 #define MT2712_MUTEX_MOD_DISP_OVL0             11
 #define MT2712_MUTEX_MOD_DISP_OVL1             12

@@ -101,12 +134,27 @@
 #define MT2712_MUTEX_SOF_DSI3                  6
 #define MT8167_MUTEX_SOF_DPI0                  2
 #define MT8167_MUTEX_SOF_DPI1                  3
+
 #define MT8183_MUTEX_SOF_DSI0                  1
 #define MT8183_MUTEX_SOF_DPI0                  2

 #define

MT8183_MUTEX_EOF_DSI0                  (MT8183_MUTEX_SOF_DSI0 << 6)
 #define
MT8183_MUTEX_EOF_DPI0                  (MT8183_MUTEX_SOF_DPI0 << 6)

+#define MT8195_MUTEX_SOF_DSI0                  1
+#define MT8195_MUTEX_SOF_DSI1                  2
+#define MT8195_MUTEX_SOF_DP_INTF0              3
+#define MT8195_MUTEX_SOF_DP_INTF1              4
+#define MT8195_MUTEX_SOF_DPI0                  6 /* for HDMI_TX */
+#define MT8195_MUTEX_SOF_DPI1                  5 /* for digital
video out */
+
+#define
MT8195_MUTEX_EOF_DSI0                  (MT8195_MUTEX_SOF_DSI0 << 7)
+#define
MT8195_MUTEX_EOF_DSI1                  (MT8195_MUTEX_SOF_DSI1 << 7)
+#define
MT8195_MUTEX_EOF_DP_INTF0              (MT8195_MUTEX_SOF_DP_INTF0
<< 7)
+#define
MT8195_MUTEX_EOF_DP_INTF1              (MT8195_MUTEX_SOF_DP_INTF1
<< 7)
+#define
MT8195_MUTEX_EOF_DPI0                  (MT8195_MUTEX_SOF_DPI0 << 7)
+#define
MT8195_MUTEX_EOF_DPI1                  (MT8195_MUTEX_SOF_DPI1 << 7)
+
 struct mtk_mutex {
        int id;
        bool claimed;

@@ -120,6 +168,9 @@ enum mtk_mutex_sof_id {
        MUTEX_SOF_DPI1,
        MUTEX_SOF_DSI2,
        MUTEX_SOF_DSI3,
+       MUTEX_SOF_DP_INTF0,
+       MUTEX_SOF_DP_INTF1,
+       DDP_MUTEX_SOF_MAX,
 };

 struct mtk_mutex_data {

@@ -214,7 +265,23 @@ static const unsigned int

mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
        [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
 };

-static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] =
{
+       [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
+       [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
+       [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
+       [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
+       [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
+       [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
+       [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
+       [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+       [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
+       [DDP_COMPONENT_DSC0] =
MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
+       [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
+       [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+       [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
+};
+
+static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
        [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
        [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
        [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,

@@ -224,7 +291,7 @@ static const unsigned int

mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
        [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
 };

-static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
        [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
        [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
        [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,

@@ -232,12 +299,24 @@ static const unsigned int

mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 };

 /* Add EOF setting so overlay hardware can receive frame done irq
*/
-static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
        [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
        [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
        [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 |
MT8183_MUTEX_EOF_DPI0,
 };

+static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
+       [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+       [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 |
MT8195_MUTEX_EOF_DSI0,
+       [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 |
MT8195_MUTEX_EOF_DSI1,
+       [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 |
MT8195_MUTEX_EOF_DPI0,
+       [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 |
MT8195_MUTEX_EOF_DPI1,
+       [MUTEX_SOF_DP_INTF0] =
+               MT8195_MUTEX_SOF_DP_INTF0 |
MT8195_MUTEX_EOF_DP_INTF0,
+       [MUTEX_SOF_DP_INTF1] =
+               MT8195_MUTEX_SOF_DP_INTF1 |
MT8195_MUTEX_EOF_DP_INTF1,

Why do you or EOF?

Regards,
Chun-Kuang.

The value of mt8195_mutex_sof will be set into this register,
#define MT8195_DISP_MUTEX0_SOF			0x2c
which is providing the source module selection of SOF(Start of Frame)
and EOF(End of Frame) in current stream(MUTEX).

MUTEX will send the EOF trigger signal to all sourcesub-module whose
EOF is selected in this register.

So I think we should or EOF to make sure sub-module cloud get both SOF
and EOF trigger signal for status checking, error handling or
debugging.

quoted

+};
+
 static const struct mtk_mutex_data mt2701_mutex_driver_data = {
        .mutex_mod = mt2701_mutex_mod,
        .mutex_sof = mt2712_mutex_sof,

@@ -275,6 +354,13 @@ static const struct mtk_mutex_data

mt8183_mutex_driver_data = {
        .no_clk = true,
 };

+static const struct mtk_mutex_data mt8195_mutex_driver_data = {
+       .mutex_mod = mt8195_mutex_mod,
+       .mutex_sof = mt8195_mutex_sof,
+       .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+       .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+};
+
 struct mtk_mutex *mtk_mutex_get(struct device *dev)
 {
        struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);

@@ -347,6 +433,9 @@ void mtk_mutex_add_comp(struct mtk_mutex

*mutex,
        case DDP_COMPONENT_DPI1:
                sof_id = MUTEX_SOF_DPI1;
                break;
+       case DDP_COMPONENT_DP_INTF0:
+               sof_id = MUTEX_SOF_DP_INTF0;
+               break;

How about MUTEX_SOF_DP_INTF1?

MUTEX_SOF_DP_INTF1 won't use in vdosys0, so it will be added at the
patch [1] in vdosys1 series.
[1] 
https://patchwork.kernel.org/project/linux-mediatek/patch/20210818091847.8060-12-nancy.lin@mediatek.com/

quoted

        default:
                if (mtx->data->mutex_mod[id] < 32) {
                        offset = DISP_REG_MUTEX_MOD(mtx->data-

quoted

mutex_mod_reg,

@@ -386,6 +475,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex

*mutex,
        case DDP_COMPONENT_DSI3:
        case DDP_COMPONENT_DPI0:
        case DDP_COMPONENT_DPI1:
+       case DDP_COMPONENT_DP_INTF0:

Ditto.

Regards,
Chun-Kuang.

Ditto.

Regards,
Jason-JH.Lin

quoted

                writel_relaxed(MUTEX_SOF_SINGLE_MODE,
                               mtx->regs +
                               DISP_REG_MUTEX_SOF(mtx->data-

quoted

mutex_sof_reg,

@@ -507,6 +597,8 @@ static const struct of_device_id

mutex_driver_dt_match[] = {
          .data = &mt8173_mutex_driver_data},
        { .compatible = "mediatek,mt8183-disp-mutex",
          .data = &mt8183_mutex_driver_data},
+       { .compatible = "mediatek,mt8195-disp-mutex",
+         .data = &mt8195_mutex_driver_data},
        {},
 };
 MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
--
2.18.0

-- 
Jason-JH Lin [off-list ref]
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