On Wed, 2020-07-29 at 18:58 +0800, Nicolas Boichat wrote:

On Wed, Jul 29, 2020 at 4:44 PM Weiyi Lu [off-list ref] wrote:

quoted

In all MediaTek PLL design, bit0 of CON0 register is always
the enable bit.
However, there's a special case of usbpll on MT8192.
The enable bit of usbpll is moved to bit2 of other register.
Add configurable en_reg and pll_en_bit for enable control or
default 0 where pll data are static variables.
Hence, CON0_BASE_EN could also be removed.
And there might have another special case on other chips,
the enable bit is still on CON0 register but not at bit0.

Signed-off-by: Weiyi Lu <redacted>
---
 drivers/clk/mediatek/clk-mtk.h |  2 ++
 drivers/clk/mediatek/clk-pll.c | 18 +++++++++++-------
 2 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index c3d6756..810eb97 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h

@@ -233,6 +233,8 @@ struct mtk_pll_data {
        uint32_t pcw_chg_reg;
        const struct mtk_pll_div_table *div_table;
        const char *parent_name;
+       uint32_t en_reg;
+       uint8_t pll_en_bit;
 };

 void mtk_clk_register_plls(struct device_node *node,

diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 3c79e1a..1434e99 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c

@@ -16,7 +16,6 @@
 #define REG_CON0               0
 #define REG_CON1               4

-#define CON0_BASE_EN           BIT(0)
 #define CON0_PWR_ON            BIT(0)
 #define CON0_ISO_EN            BIT(1)
 #define PCW_CHG_MASK           BIT(31)

@@ -44,6 +43,7 @@ struct mtk_clk_pll {
        void __iomem    *tuner_en_addr;
        void __iomem    *pcw_addr;
        void __iomem    *pcw_chg_addr;
+       void __iomem    *en_addr;
        const struct mtk_pll_data *data;
 };

@@ -56,7 +56,7 @@ static int mtk_pll_is_prepared(struct clk_hw *hw)
 {
        struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);

-       return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;
+       return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;
 }

 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,

@@ -247,8 +247,8 @@ static int mtk_pll_prepare(struct clk_hw *hw)
        writel(r, pll->pwr_addr);
        udelay(1);

-       r = readl(pll->base_addr + REG_CON0) | CON0_BASE_EN;
-       writel(r, pll->base_addr + REG_CON0);
+       r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit);
+       writel(r, pll->en_addr);

        r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;
        writel(r, pll->base_addr + REG_CON0);

@@ -283,9 +283,9 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
        r &= ~pll->data->en_mask;
        writel(r, pll->base_addr + REG_CON0);

-       r = readl(pll->base_addr + REG_CON0);
-       r &= ~CON0_BASE_EN;
-       writel(r, pll->base_addr + REG_CON0);
+       r = readl(pll->en_addr);
+       r &= ~BIT(pll->data->pll_en_bit);

1 line, but that'll come naturally from the change I requested in the
previous patch.

OK, I'll put it into one line in previous patch.

quoted

+       writel(r, pll->en_addr);

        r = readl(pll->pwr_addr) | CON0_ISO_EN;
        writel(r, pll->pwr_addr);

@@ -327,6 +327,10 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
                pll->tuner_addr = base + data->tuner_reg;
        if (data->tuner_en_reg)
                pll->tuner_en_addr = base + data->tuner_en_reg;
+       if (data->en_reg)
+               pll->en_addr = base + data->en_reg;
+       else
+               pll->en_addr = pll->base_addr + REG_CON0;

Don't you need to set pll->data->pll_en_bit to CON0_BASE_EN here?
(which probably means that you need to add a pll->en_bit field to
struct mtk_clk_pll)

Because all mtk_clk_pll data are static variables, en_bit would be 0 if
NO value assigned.

r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit);
writel(r, pll->en_addr);

quoted

        pll->hw.init = &init;
        pll->data = data;

--
1.8.1.1.dirty

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