From 393f445ab899abaf5d60a55a54f242c430507047 Mon Sep 17 00:00:00 2001
From: Jason Wang <redacted>
Date: Thu, 14 Oct 2010 10:08:07 +0800
Subject: [PATCH] spi/omap2_mcspi: disable channel after TX_ONLY transfer in
PIO mode

In TX_ONLY transfer, the SPI controller can also receive data
simultaneously and saves them in rx register. After the TX_ONLY
transfer, the rx register will hold random data received during
last tx transaction.

If the next transfer is RX_ONLY, this random data has
the possibility to affect this transfer like this:

 If the spi controller is changed from TX_ONLY to RX_ONLY mode,
 The random data makes the rx register full imediately and
 triggers a dummy write (in SPI RX_ONLY transfer, we need a dummy
 write to trigger the first transaction).

 So the first data received in RX_ONLY transfer will be that
 random data instead of something meaningfug.

We can avoid this by a Disable/reenable toggle of the spi channel
after the TX_ONLY transfer, since it purges the rx register.

Signed-off-by: Jason Wang <redacted>
---
drivers/spi/omap2_mcspi.c |    6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index b3a94ca..43fab41 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c

@@ -644,6 +644,12 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct

spi_transfer *xfer)
              } else if (mcspi_wait_for_reg_bit(chstat_reg,
                              OMAP2_MCSPI_CHSTAT_EOT) < 0)
                      dev_err(&spi->dev, "EOT timed out\n");
+
+               /* disable chan to purge rx datas received in TX_ONLY
transfer,
+                * otherwise these rx datas will affect the direct following
+                * RX_ONLY transfer.
+                */
+               omap2_mcspi_set_enable(spi, 0);
      }
out:
      omap2_mcspi_set_enable(spi, 1);
--
1.5.6.5