On Sat, 25 Sep 2021 10:05:45 +0800
Cai Huoqing [off-list ref] wrote:

The NXP i.MX 8QuadXPlus SOC has a new ADC IP, so add
driver support for this ADC.

Signed-off-by: Cai Huoqing <redacted>

Hi Cai Huoqing,

Having had a 'final' read through of the driver, I am basically happy
to merge this after Fabio has had time for another look (plus anyone else
who wishes to of course!) 

There were a few minor things inline though that I'll tidy up whilst applying.
If you do a v7 for some other reason please sort these out as well.

Thanks,

Jonathan

...

+#define IMX8QXP_ADR_ADC_TCTRL(tid)	(0xc0 + tid * 4)
+#define IMX8QXP_ADR_ADC_CMDH(cid)	(0x100 + cid * 8)
+#define IMX8QXP_ADR_ADC_CMDL(cid)	(0x104 + cid * 8)

In macros, it is always a good idea to put brackets around
any use of parameters so as to avoid potential odd issues
due to operator precedence.

(0xc0 + (tid) * 4)

+#define IMX8QXP_ADR_ADC_RESFIFO		0x300
+#define IMX8QXP_ADR_ADC_TST		0xffc

...

+
+struct imx8qxp_adc {
+	struct device *dev;
+	void __iomem *regs;
+	struct clk *clk;
+	struct clk *ipg_clk;
+	struct regulator *vref;
+	struct mutex lock;

A lock should have documentation to identify what it's precise scope is.
I can add

/* Serialise ADC channel reads */
above the lock definition whilst applying if you aren't doing a v7 for
other reasons.

+	struct completion completion;
+};

...

+
+static irqreturn_t imx8qxp_adc_isr(int irq, void *dev_id)
+{
+	struct imx8qxp_adc *adc = dev_id;
+

Really minor, but the blank line here doesn't help readability much and
is inconsistent with the rest of the driver.  I might remove this whilst
applying if nothing else comes up.

+	u32 fifo_count;
+
+	fifo_count = FIELD_GET(IMX8QXP_ADC_FCTRL_FCOUNT_MASK,
+			       readl(adc->regs + IMX8QXP_ADR_ADC_FCTRL));
+
+	if (fifo_count)
+		complete(&adc->completion);
+
+	return IRQ_HANDLED;
+}
+

...