Re: Disabling Command Completion Coalescing (CCC) in SATA AHCI
From: Pallav Bose <hidden>
Date: 2011-06-01 18:26:16
On Tue, May 24, 2011 at 1:16 AM, Pallav Bose [off-list ref] wrote:
Another question that I have is regarding my second experiment. It's as follows: Create a bio structure in my driver and call the __make_request() function of the lower level driver. Only one 2560 bytes write request is sent from my driver. Once this write is serviced, an interrupt is generated which is intercepted by do_IRQ(). Finally, the function blk_complete_request() is called. Keep in mind that we are still in the top half of the interrupt handler. Now, we compose another struct bio in blk_complete_request() and call the __make_request() function. We record a timestamp at this point (say T0). When the request completion callback is obtained, we record another timestamp (call it T1). The difference - T1 - T0 - is always above 1 millisec. This experiment was repeated numerous times, and each time, the destination sector affected this difference - T1 - T0. It was observed that if the destination sectors are separated by approximately 350 sectors, the time difference is about 1.2 millisec (never below 1 millisec) for requests of size 2560 bytes. My understanding is that since the destination sectors of consecutive requests have been separated by a fairly large amount, by the time the next request is issued, the requested sector would be almost below the disk head and thus the write should happen immediately and T1 - T0 should be small (at least < 1 millisec). The Serial ATA AHCI 1.3 Specification (page 114) states that: When a software specified number of commands have completed or **a software specified timeout has expired, an interrupt is generated by hardware to allow software to process completed commands.** I assumed that this timer maybe the reason why the latency of each request is above 1 millisec; that's why I wanted to disable CCC. Now since CCC is out of the picture, what could be the reason why the latency is above 1 millisec always? Can we do better? Regards, Pallav
Any further thoughts on why the latency is above 1 millisec in the experiment that I have described above? Thanks, Pallav