Re: [PATCH v1] i2c: tegra: Fix i2c_writesl() to use writel() instead of writesl()
From: Sowjanya Komatineni <skomatineni@nvidia.com>
Date: 2021-01-12 16:57:39
Also in:
linux-tegra, lkml
On 1/12/21 1:32 AM, David Laight wrote:
From: Sowjanya Komatineniquoted
Sent: 11 January 2021 17:38...quoted
Using writesl() for filling TX_FIFO causing silent hang immediate on any i2c register access after filling FIFO with 8 words and some times with 6 words as well. So couldn't INTERRUPT_STATUS registers to check for TX FIFO Overflows when this silent hang happens. Tried to read thru back-door (JTAG path) but could not connect to JTAG either. Looks like Tegra chip is in some weird state. But using writel() followed by i2c_readl helps. Not sure if any thing related to register access delay or some other issue.How much does the i2c_read() slow down the transfer? If the device is PCIe it is probably significant. If the underlying problem is that the Tegra chip can't handle back to back writes to the tx fifo maybe there are other solutions! 1) Send it back and ask for a working chip :-) 2) Maybe an interleaved write will slow things down enough? It may be worth testing back to back writes to other registers to see if it is a problem that is specific to the tx fifo. David - Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK Registration No: 1397386 (Wales)
This is a known hardware bug with VI I2C controller which is under host1x where immediate multiple writes to TX FIFO register gets stuck and reading from a register allows them to be flushed out. VI I2C is dedicated for camera sensors or HDMI2CSI bridge.