Re: [PATCH v2] x86/hyperv: add comment describing TSC_INVARIANT_CONTROL MSR setting bit 0
From: Wei Liu <wei.liu@kernel.org>
Date: 2021-07-16 14:53:15
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On Fri, Jul 16, 2021 at 07:02:45PM +0530, Ani Sinha wrote:
Commit dce7cd62754b5 ("x86/hyperv: Allow guests to enable InvariantTSC")
added the support for HV_X64_MSR_TSC_INVARIANT_CONTROL. Setting bit 0
of this synthetic MSR will allow hyper-v guests to report invariant TSC
CPU feature through CPUID. This comment adds this explanation to the code
and mentions where the Intel's generic platform init code reads this
feature bit from CPUID. The comment will help developers understand how
the two parts of the initialization (hyperV specific and non-hyperV
specific generic hw init) are related.
Signed-off-by: Ani Sinha <redacted>Applied to hyperv-next. Thanks.