Thread (23 messages) 23 messages, 5 authors, 2021-10-19

Re: [PATCH v6 5/6] dt-bindings: mfd: Add Delta TN48M CPLD drivers bindings

From: Robert Marko <robert.marko@sartura.hr>
Date: 2021-10-19 10:49:23
Also in: linux-devicetree, lkml

On Tue, Oct 19, 2021 at 3:40 AM Andrew Lunn [off-list ref] wrote:
quoted
The SFP driver requires GPIO-s, it only knows how to use GPIO-s, and
its a generic driver,
it covers any device that has an SFP port that is implemented per spec.
So, I cannot just extend it to suit my devices needs and I don't see
how can I extend it in
a generic manner so that it controls the pins directly via a regmap
for example, especially since
each switch has a different number of SFP ports and thus pins and a
different register layout.

I have added Andrew Lunn as he is one of the maintainers of PHYLIB
under which the SFP driver
is, he may have some input on how to proceed with this.

I honestly think that we have some kind of misunderstanding here and
look forward to resolving it.
Hi Robert

Can you describe your hardware and regmap in a bit more detail. What
do these registers look like? How do they map to the SFP cage pins?
Hi Andrew,
This board is simple as it only has 4 SFP ports so they have split the
respective
pins into individual registers per their purpose.

So TX disable pins have their own 8bit register and they map pins
using individual bits.
This is how the register looks:
+-----+---------------+-----+-------------------+---------------+
| Bit |     Name      | R/W |    Description    | Default value |
+-----+---------------+-----+-------------------+---------------+
| 7:4 | Reserved         | R/W | Not used                |     0 |
| 3   | TX_Disable_52 | R/W | Enable/disable       |     0 |
| 2   | TX_Disable_51 | R/W | SFP TX transmiter |     0 |
| 1   | TX_Disable_50 | R/W | 1 = TX off               |     0 |
| 0   | TX_Disable_49 | R/W | 0 = TX on               |     0 |
+-----+---------------+-----+-------------------+---------------+

Presence and LOS pins also have their respective registers in
the same format.
So you can see that the register bits map directly to the SFP cage pins.

Regards,
Robert
          Andrew


-- 
Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
10000 Zagreb, Croatia
Email: robert.marko@sartura.hr
Web: www.sartura.hr
Keyboard shortcuts
hback out one level
jnext message in thread
kprevious message in thread
ldrill in
Escclose help / fold thread tree
?toggle this help