Linus Walleij writes:

Hi Lars,

a new version of the patch set arrives while I'm reviewing, haha :D

Well, luckily not too much changed per Rob's input.

On Wed, Oct 7, 2020 at 1:12 PM Lars Povlsen [off-list ref] wrote:

quoted

This adds DT bindings for the Microsemi/Microchip SGPIO controller,
bindings microchip,sparx5-sgpio, mscc,ocelot-sgpio and
mscc,luton-sgpio.

Signed-off-by: Lars Povlsen <redacted>

(...)

quoted

+      reg:
+        description: |
+          The GPIO bank number. "0" is designates the input pin bank,
+          "1" the output bank.
+        maxItems: 1

Excellent.

quoted

+      '#gpio-cells':
+        const: 3

So I thought you needed three cells exactly because the
middle cell would get you the bank. That you now have in
reg. So what about using the standard twocell?

I think I answered that in the 'v3 2/3' reply.

Basically the pins are addressed with two indices, and there are good
reasons to expose these to the GPIO cells, f.ex. hardware documentation
cross reference.

---Lars

Yours,
Linus Walleij

-- 
Lars Povlsen,
Microchip