Re: [PATCH v2 3/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LPCHC)
From: Joel Stanley <joel@jms.id.au>
Date: 2016-11-03 23:06:52
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linux-arm-kernel, linux-devicetree, lkml
On Thu, Nov 3, 2016 at 1:07 AM, Andrew Jeffery [off-list ref] wrote:
quoted hunk ↗ jump to hunk
The Aspeed LPC Host Controller is presented as a syscon device to arbitrate access by LPC and pinmux drivers. LPC pinmux configuration on fifth generation SoCs depends on bits in both the System Control Unit and the LPC Host Controller. Signed-off-by: Andrew Jeffery <redacted> --- Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpchc.txtdiff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt new file mode 100644 index 000000000000..792651488c3d --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt@@ -0,0 +1,17 @@ +* Device tree bindings for the Aspeed LPC Host Controller (LPCHC)
I had to check the data sheet for that acronym. They call the registers LHC. I somewhat prefer that name, but if you're happy with it as-is then that's fine. I assume this is not an issue on the g4/ast2400?
+
+The LPCHC registers configure LPC behaviour between the BMC and the host
+system. The LPCHC also participates in pinmux requests on g5 SoCs and is
+therefore considered a syscon device.
+
+Required properties:
+- compatible: "aspeed,ast2500-lpchc", "syscon"
+- reg: contains offset/length value of the LPCHC memory
+ region.
+
+Example:
+
+lpchc: lpchc@1e7890a0 {
+ compatible = "aspeed,ast2500-lpchc", "syscon";
+ reg = <0x1e7890a0 0xc4>;Where's the 0xc4 come from? I can see 9 registers, which would mean the length should be 0x24? Cheers, Joel