On 20 June 2018 at 00:29, Bjorn Helgaas [off-list ref] wrote:
Minor subject nit: From the caller's point of view, we must convert a bus
address to a resource *always* (the caller has no knowledge of "whether it
is translated by the host bridge").
On Fri, May 18, 2018 at 10:17:51AM -0400, Sinan Kaya wrote:
quoted
A host bridge is allowed to remap BAR addresses using _TRA attribute in
_CRS windows.
Also, _TRA/_CRS are ACPI-specific terms and non-ACPI host bridges can
also do the same sort of translation. Another trivial nit.
quoted
pci_bus 0000:00: root bus resource [mem 0x80100100000-0x8011fffffff window] (bus address [0x00100000-0x1fffffff])
pci 0000:02:00.0: reg 0x10: [mem 0x8011e000000-0x8011effffff]
When a VGA device is behind such a host bridge and the resource is
translated efifb driver is trying to do ioremap against bus address
rather than the resource address and is failing to probe.
efifb: probing for efifb
efifb: cannot reserve video memory at 0x1e000000
efifb: framebuffer at 0x1e000000, using 1920k, total 1875k
efifb: mode is 800x600x32, linelength200, pages=1
efifb: scrolling: redraw
efifb: Truecolor: size=8:8:8:8, shift$:16:8:0
Use the host bridge offset information to convert bus address to
resource address in the fixup.
Signed-off-by: Sinan Kaya <redacted>
Reviewed-by: Bjorn Helgaas <bhelgaas@google.com>
Thanks a lot for fixing this!
Apologies for only bringing this up now, but I think this patch is
wrong after all.
screen_info.lfb_base is supposed to be a CPU address, and so
translating it like this is wrong. If you end up with a PCI address
here, you have made a mistake in hacking support for PCI outbound
translations into UEFI. Other users such as UEFI itself or GRUB will
treat this as a CPU physical address as well, so the kernel should not
treat it any differently.
From: Sinan Kaya <hidden> Date: 2018-06-22 13:53:05
Hi Ard,
On 6/22/2018 7:21 AM, Ard Biesheuvel wrote:
Apologies for only bringing this up now, but I think this patch is
wrong after all.
screen_info.lfb_base is supposed to be a CPU address, and so
translating it like this is wrong. If you end up with a PCI address
here, you have made a mistake in hacking support for PCI outbound
translations into UEFI. Other users such as UEFI itself or GRUB will
treat this as a CPU physical address as well, so the kernel should not
treat it any differently.
The behavior I'm seeing is from a UEFI BIOS vendor. I did not write the
code for it...
I was asked to debug it.
I'd like to dive into your statement about UEFI and GRUB using this address
as physical addresses.
AFAIK, all PCI outbound requests go through PCI IO protocol in UEFI and the
translation information is hidden inside the UEFI PCI Host Bridge driver.
Drivers are not allowed to access PCI resources directly especially as a
memory mapped address.
This particular vendor is programming the BAR address into the GOP protocol.
Since the host bridge driver is doing a translation, we are hitting this
issue.
Is there a UEFI spec reference about the definition of this field?
Sinan
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
On 22 June 2018 at 15:52, Sinan Kaya [off-list ref] wrote:
Hi Ard,
On 6/22/2018 7:21 AM, Ard Biesheuvel wrote:
quoted
Apologies for only bringing this up now, but I think this patch is
wrong after all.
screen_info.lfb_base is supposed to be a CPU address, and so
translating it like this is wrong. If you end up with a PCI address
here, you have made a mistake in hacking support for PCI outbound
translations into UEFI. Other users such as UEFI itself or GRUB will
treat this as a CPU physical address as well, so the kernel should not
treat it any differently.
The behavior I'm seeing is from a UEFI BIOS vendor. I did not write the
code for it...
I was asked to debug it.
I'd like to dive into your statement about UEFI and GRUB using this address
as physical addresses.
AFAIK, all PCI outbound requests go through PCI IO protocol in UEFI and the
translation information is hidden inside the UEFI PCI Host Bridge driver.
Drivers are not allowed to access PCI resources directly especially as a
memory mapped address.
This particular vendor is programming the BAR address into the GOP protocol.
Since the host bridge driver is doing a translation, we are hitting this
issue.
Is there a UEFI spec reference about the definition of this field?
Yes, it is part of the PCI I/O protocol definition. FrameBufferBase is
described as
"""
Base address of graphics linear frame buffer. Info contains
information required to allow software to draw directly to the
frame buffer without using Blt().Offset zero in
FrameBufferBase represents the upper left pixel of the
display.
"""
On 22 June 2018 at 15:55, Ard Biesheuvel [off-list ref] wrote:
On 22 June 2018 at 15:52, Sinan Kaya [off-list ref] wrote:
quoted
Hi Ard,
On 6/22/2018 7:21 AM, Ard Biesheuvel wrote:
quoted
Apologies for only bringing this up now, but I think this patch is
wrong after all.
screen_info.lfb_base is supposed to be a CPU address, and so
translating it like this is wrong. If you end up with a PCI address
here, you have made a mistake in hacking support for PCI outbound
translations into UEFI. Other users such as UEFI itself or GRUB will
treat this as a CPU physical address as well, so the kernel should not
treat it any differently.
The behavior I'm seeing is from a UEFI BIOS vendor. I did not write the
code for it...
I was asked to debug it.
I'd like to dive into your statement about UEFI and GRUB using this address
as physical addresses.
AFAIK, all PCI outbound requests go through PCI IO protocol in UEFI and the
translation information is hidden inside the UEFI PCI Host Bridge driver.
Drivers are not allowed to access PCI resources directly especially as a
memory mapped address.
This particular vendor is programming the BAR address into the GOP protocol.
Since the host bridge driver is doing a translation, we are hitting this
issue.
Is there a UEFI spec reference about the definition of this field?
Yes, it is part of the PCI I/O protocol definition. FrameBufferBase is
described as
"""
Base address of graphics linear frame buffer. Info contains
information required to allow software to draw directly to the
frame buffer without using Blt().Offset zero in
FrameBufferBase represents the upper left pixel of the
display.
"""
I just tried AMD Radeon and NVidia graphics cards on a system with
non-1:1 mapped MMIO windows, and in both cases, the GOP protocol
structure is populated correctly, i.e., using the CPU address not the
PCIe address.
EDK2 only recently gained support for MMIO translation in the host
bridge driver, so I so wonder if this is a platform issue rather than
a driver issue. It may be worth a try to dump the results of
GetBarAttributes() of all PCI I/O protocol instances (either in UEFI
or in the stub), to double check that the correct values are returned.
From: Sinan Kaya <hidden> Date: 2018-06-22 18:30:17
On 6/22/2018 2:01 PM, Ard Biesheuvel wrote:
quoted
Yes, it is part of the PCI I/O protocol definition. FrameBufferBase is
described as
"""
Base address of graphics linear frame buffer. Info contains
information required to allow software to draw directly to the
frame buffer without using Blt().Offset zero in
FrameBufferBase represents the upper left pixel of the
display.
"""
I just tried AMD Radeon and NVidia graphics cards on a system with
non-1:1 mapped MMIO windows, and in both cases, the GOP protocol
structure is populated correctly, i.e., using the CPU address not the
PCIe address.
EDK2 only recently gained support for MMIO translation in the host
bridge driver, so I so wonder if this is a platform issue rather than
a driver issue. It may be worth a try to dump the results of
GetBarAttributes() of all PCI I/O protocol instances (either in UEFI
or in the stub), to double check that the correct values are returned.
Thanks for checking out other platforms. I'll mark the issue as a BIOS
issue and bounce your feedback to the BIOS provider.
Let's hold onto this patch for the moment.
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
On 22 June 2018 at 20:30, Sinan Kaya [off-list ref] wrote:
On 6/22/2018 2:01 PM, Ard Biesheuvel wrote:
quoted
quoted
Yes, it is part of the PCI I/O protocol definition. FrameBufferBase is
described as
"""
Base address of graphics linear frame buffer. Info contains
information required to allow software to draw directly to the
frame buffer without using Blt().Offset zero in
FrameBufferBase represents the upper left pixel of the
display.
"""
I just tried AMD Radeon and NVidia graphics cards on a system with
non-1:1 mapped MMIO windows, and in both cases, the GOP protocol
structure is populated correctly, i.e., using the CPU address not the
PCIe address.
EDK2 only recently gained support for MMIO translation in the host
bridge driver, so I so wonder if this is a platform issue rather than
a driver issue. It may be worth a try to dump the results of
GetBarAttributes() of all PCI I/O protocol instances (either in UEFI
or in the stub), to double check that the correct values are returned.
Thanks for checking out other platforms. I'll mark the issue as a BIOS
issue and bounce your feedback to the BIOS provider.
I screwed up my testing, unfortunately. Both the public AMD GOP driver
I tried, and the Nvidia GT218 under x86 emulation break when using
MMIO translation. However, GraphicsOutputDxe in the EDK2 tree gets it
right, and uses PciIo->GetBarAttributes() to get the address of the
framebuffer region, which will return the CPU address not the PCI
address.
Let's hold onto this patch for the moment.
Yes. I'd like to get this resolved as well, but if the drivers are
dereferencing BAR values as CPU addresses, this is unlikely to be the
only thing that is broken under outbound translation.
On 22 June 2018 at 21:29, Ard Biesheuvel [off-list ref] wrote:
On 22 June 2018 at 20:30, Sinan Kaya [off-list ref] wrote:
quoted
On 6/22/2018 2:01 PM, Ard Biesheuvel wrote:
quoted
quoted
Yes, it is part of the PCI I/O protocol definition. FrameBufferBase is
described as
"""
Base address of graphics linear frame buffer. Info contains
information required to allow software to draw directly to the
frame buffer without using Blt().Offset zero in
FrameBufferBase represents the upper left pixel of the
display.
"""
I just tried AMD Radeon and NVidia graphics cards on a system with
non-1:1 mapped MMIO windows, and in both cases, the GOP protocol
structure is populated correctly, i.e., using the CPU address not the
PCIe address.
EDK2 only recently gained support for MMIO translation in the host
bridge driver, so I so wonder if this is a platform issue rather than
a driver issue. It may be worth a try to dump the results of
GetBarAttributes() of all PCI I/O protocol instances (either in UEFI
or in the stub), to double check that the correct values are returned.
Thanks for checking out other platforms. I'll mark the issue as a BIOS
issue and bounce your feedback to the BIOS provider.
I screwed up my testing, unfortunately. Both the public AMD GOP driver
I tried, and the Nvidia GT218 under x86 emulation break when using
MMIO translation. However, GraphicsOutputDxe in the EDK2 tree gets it
right, and uses PciIo->GetBarAttributes() to get the address of the
framebuffer region, which will return the CPU address not the PCI
address.
quoted
Let's hold onto this patch for the moment.
Yes. I'd like to get this resolved as well, but if the drivers are
dereferencing BAR values as CPU addresses, this is unlikely to be the
only thing that is broken under outbound translation.
Note that this was fixed fairly recently in EDK2, so BIOS vendors
providing UEFI firmware for ARM platforms with outbound MMIO
translation should probably incorporate this EDK2 patch
commit dc080d3b61e570e7a3163fc24afa6f8388d0c0bf
Author: Heyi Guo [off-list ref]
Date: Thu Feb 8 11:13:27 2018 +0800
MdeModulePkg/PciBus: return CPU address for GetBarAttributes
According to UEFI spec 2.7, PciIo->GetBarAttributes should return host
address (CPU view ddress) rather than device address (PCI view
address), and
device address = host address + address translation offset,
so we subtract translation from device address before returning.
Note that this is not the only MMIO translation related change made by
Heyi Guo to the generic PCI host bridge and bus drivers, but given
that those did not support MMIO translation at all, I take it your
affected platforms will already have their own changes to accommodate
this.
On 22 June 2018 at 21:29, Ard Biesheuvel [off-list ref]
wrote:
quoted
On 22 June 2018 at 20:30, Sinan Kaya [off-list ref] wrote:
quoted
On 6/22/2018 2:01 PM, Ard Biesheuvel wrote:
quoted
quoted
Yes, it is part of the PCI I/O protocol definition. FrameBufferBase
is
described as
"""
Base address of graphics linear frame buffer. Info contains
information required to allow software to draw directly to the
frame buffer without using Blt().Offset zero in
FrameBufferBase represents the upper left pixel of the
display.
"""
I just tried AMD Radeon and NVidia graphics cards on a system with
non-1:1 mapped MMIO windows, and in both cases, the GOP protocol
structure is populated correctly, i.e., using the CPU address not
the
PCIe address.
EDK2 only recently gained support for MMIO translation in the host
bridge driver, so I so wonder if this is a platform issue rather
than
a driver issue. It may be worth a try to dump the results of
GetBarAttributes() of all PCI I/O protocol instances (either in UEFI
or in the stub), to double check that the correct values are
returned.
Thanks for checking out other platforms. I'll mark the issue as a
BIOS
issue and bounce your feedback to the BIOS provider.
I screwed up my testing, unfortunately. Both the public AMD GOP driver
I tried, and the Nvidia GT218 under x86 emulation break when using
MMIO translation. However, GraphicsOutputDxe in the EDK2 tree gets it
right, and uses PciIo->GetBarAttributes() to get the address of the
framebuffer region, which will return the CPU address not the PCI
address.
quoted
Let's hold onto this patch for the moment.
Yes. I'd like to get this resolved as well, but if the drivers are
dereferencing BAR values as CPU addresses, this is unlikely to be the
only thing that is broken under outbound translation.
Note that this was fixed fairly recently in EDK2, so BIOS vendors
providing UEFI firmware for ARM platforms with outbound MMIO
translation should probably incorporate this EDK2 patch
commit dc080d3b61e570e7a3163fc24afa6f8388d0c0bf
Author: Heyi Guo [off-list ref]
Date: Thu Feb 8 11:13:27 2018 +0800
MdeModulePkg/PciBus: return CPU address for GetBarAttributes
According to UEFI spec 2.7, PciIo->GetBarAttributes should return
host
address (CPU view ddress) rather than device address (PCI view
address), and
device address = host address + address translation offset,
so we subtract translation from device address before returning.
Note that this is not the only MMIO translation related change made by
Heyi Guo to the generic PCI host bridge and bus drivers, but given
that those did not support MMIO translation at all, I take it your
affected platforms will already have their own changes to accommodate
this.
Platform has been doing mmio translation for quite a while. Because all
accesses go through pci io protocol, the rest of the UEFI never needed
to be aware of bar address or do direct access.
This is the first time I hear of direct access. Maybe, GOP is a special
case.
I started copying your response to the bios vendor.
They are probably missing that patch. I will pass it along.
From: Sinan Kaya <hidden> Date: 2018-06-25 17:28:20
On 6/25/2018 11:52 AM, okaya@codeaurora.org wrote:
quoted
Note that this is not the only MMIO translation related change made by
Heyi Guo to the generic PCI host bridge and bus drivers, but given
that those did not support MMIO translation at all, I take it your
affected platforms will already have their own changes to accommodate
this.
Platform has been doing mmio translation for quite a while. Because all accesses go through pci io protocol, the rest of the UEFI never needed to be aware of bar address or do direct access.
This is the first time I hear of direct access. Maybe, GOP is a special case.
I started copying your response to the bios vendor.
They are probably missing that patch. I will pass it along.
I was informed that they fixed the issue in BIOS by presenting CPU physical
address instead of PCI bus address in FrameBufferBase of the AST GOP UEFI driver.
We can drop this patch now.
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
On 25 June 2018 at 19:28, Sinan Kaya [off-list ref] wrote:
On 6/25/2018 11:52 AM, okaya@codeaurora.org wrote:
quoted
quoted
Note that this is not the only MMIO translation related change made by
Heyi Guo to the generic PCI host bridge and bus drivers, but given
that those did not support MMIO translation at all, I take it your
affected platforms will already have their own changes to accommodate
this.
Platform has been doing mmio translation for quite a while. Because all accesses go through pci io protocol, the rest of the UEFI never needed to be aware of bar address or do direct access.
This is the first time I hear of direct access. Maybe, GOP is a special case.
I started copying your response to the bios vendor.
They are probably missing that patch. I will pass it along.
I was informed that they fixed the issue in BIOS by presenting CPU physical
address instead of PCI bus address in FrameBufferBase of the AST GOP UEFI driver.
We can drop this patch now.
Excellent! Thanks for following up with the vendor ...
From: Sinan Kaya <hidden> Date: 2018-06-25 17:31:37
On 6/25/2018 1:29 PM, Ard Biesheuvel wrote:
quoted
quoted
Platform has been doing mmio translation for quite a while. Because all accesses go through pci io protocol, the rest of the UEFI never needed to be aware of bar address or do direct access.
This is the first time I hear of direct access. Maybe, GOP is a special case.
I started copying your response to the bios vendor.
They are probably missing that patch. I will pass it along.
I was informed that they fixed the issue in BIOS by presenting CPU physical
address instead of PCI bus address in FrameBufferBase of the AST GOP UEFI driver.
We can drop this patch now.
Excellent! Thanks for following up with the vendor ...
Sure, appreciate the help.
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.