Jonghun Han [off-list ref] writes:

Tomi Valkeinen wrote:

2010/11/30 Tomi Valkeinen [off-list ref]:

quoted

On Tue, 2010-11-30 at 12:29 +0530, ext Hiremath, Vaibhav wrote:

quoted

quoted

-----Original Message-----
From: Paul Mundt [mailto:lethal@linux-sh.org]
Sent: Tuesday, November 30, 2010 12:10 PM
To: Ville Syrj?l?
Cc: Hiremath, Vaibhav; M?ns Rullg?rd; linux-omap@vger.kernel.org; linux-
fbdev@vger.kernel.org
Subject: Re: OMAP:DSS: possible bug in WAITFOR_VSYNC ioctl

On Tue, Nov 30, 2010 at 03:34:40PM +0900, Paul Mundt wrote:

<snip>

quoted

OMAP has user writeable shadow registers and hidden real registers for
display controller. The shadow registers are latched to real registers
on VFP, but only if GO bit has been set. The GO bit is cleared by the HW
when latching has been done.

If the GO bit is set, we cannot touch the shadow registers because we
don't know when the VFP  will happen. That's why there's additionally a
SW cache for the config, so that we don't need to block when the GO bit
is up and the user wants to change the config. The driver "flushes" the
SW config to real registers in VSYNC interrupt handler.

Does the driver flush the config to real register directly not a
shadow register in VSYNC ISR? Does it mean display controller use
the config flushed to the real register from the VSYNC ?

The hardware latches the shadow registers to the active registers at
start of VFP.

I don't know OMAP in detail. But as I know other SoCs also work like it.

Can Go bit is cleared by SW?

No.

And does each overlay(FB) have its own Go bit?

No.  There is one GO bit per video output, i.e. one each for LCD and TV.

-- 
Måns Rullgård
mans@mansr.com