On Wed, Jan 31, 2007 at 03:58:11PM -0600, Paul A. Clarke wrote:

Ville Syrjälä wrote:

quoted

On Tue, Jan 30, 2007 at 02:22:37PM -0600, Paul A. Clarke wrote:
snip...

quoted

+				/* DVI PLL preferred for frequencies up to panellink max, standard PLL
otherwise */
+				if (fout >= MINFO->max_pixel_clock_panellink) tmp = 0;
+				else tmp =
+					M1064_XDVICLKCTRL_DVIDATAPATHSEL |
+					M1064_XDVICLKCTRL_C1DVICLKSEL |
+					M1064_XDVICLKCTRL_C1DVICLKEN |

Shouldn't this check which CRTC is driving the DVI?

If I read the code correctly, I don't see any way this code gets invoked for CRTC2.  __g450_setclk() is only called by 
matroxfb_g450_setclk(), which is in turn called in 8 places:
- 2 with pll == M_VIDEO_PLL (a different case in the enclosing switch)
- 1 with pll == M_SYSTEM_PLL (a different case in the enclosing switch)
- 3 which if (m->crtc != MATROXFB_SRC_CRTC1) then pll == M_VIDEO_PLL
- 2 with M_PIXEL_PLL_A and M_PIXEL_PLL_B (once each) at init time to set legacy VGA clocks with both CRTCs disabled

I see. It seems to always use VIDPLL with CRTC2. So if DVICLK is to be 
used with CRTC2 it apparently needs to be added in the VIDPLL case. 
Hmmm. I wonder if the code even supports CRTC2+DVI because the CRTC2 
code seems to leave the C2PIXCLK selection to PCICLK if CRTC2 drives DVI 
only. Did you try to map CRTC2 to DVI?

Unfortunately I don't have a TFT so I can't actually test this stuff. 
Probably time to get one... :)

-- 
Ville Syrjälä
syrjala@sci.fi
http://www.sci.fi/~syrjala/

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